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MAX3891
16:1 Serializer, 3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs

Low-Power, Low-Cost Transceiver Chipset


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Status
All versions are No Longer Available.

Description
FULL DATA SHEET (PDF, 528kB)
Download this datasheet in PDF formatDownload   Send this datasheet to any email addressE-Mail
The MAX3891 serializer converts 16-bit wide, 155Mbps parallel data to 2.5Gbps serial data in ATM and SDH/SONET applications. The MAX3891 is ideal for interfacing with high-speed digital circuitry. This device accepts single-ended LVPECL data inputs and delivers differential LVPECL data and clock outputs. An internal 2.5Gbps serial clock, synthesized by a fully integrated PLL that accepts multiple input reference clock rates, retimes the output data stream. The MAX3891 operates from a single +3.3V supply and accepts differential LVPECL reference clock rates of 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz. A CML loopback data output is provided to facilitate system diagnostic testing. The MAX3891 is available in the extended temperature range (-40°C to +85°C) in a 64-pin TQFP exposed pad (EP) package.

An evaluation kit is available:  MAX3891EVKIT  

Key Features   Applications/Uses
  • Single +3.3V Supply
  • 495mW Power Consumption
  • Exceeds ANSI, ITU, and Bellcore Specifications
  • 155Mbps (16-bit wide) Parallel to 2.5Gbps Serial Conversion
  • Clock Synthesis for 2.5Gbps
  • Multiple Clock Reference Frequencies (155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz)
  • Additional High-Speed Output for System Loopback Testing
  • Single-Ended PECL Data Inputs
  • Differential PECL Clock Inputs and Serial Data Outputs

 
  • 2.5Gbps Access Nodes
  • 2.5Gbps SDH/SONET Transmission Systems
  • Add/Drop Multiplexers
  • ATM Backplanes
  • Digital Cross-Connects

    Diagram
    MAX3891: Typical Application Circuit
    Typical Application Circuit

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    Document Ref.: 19-1963; Rev 0; 2001-02-01
    This page last modified: 2007-06-15


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