The MAX3831/MAX3832 are 4:1 multiplexers (muxes) and 1:4 demultiplexers (demuxes) with automatic channel alignment. Operating from a single +3.3V supply, the mux receives four parallel, 622Mbps SDH/SONET channels. These channels are bit interleaved to generate a serial data stream of 2.488Gbps for interfacing to an optical or an electrical driver. A 10-bit-wide elastic buffer tolerates up to ±7.5ns skew between any parallel data input and the reference clock. An external 155MHz reference clock is required for the on-chip PLL to synthesize a high-frequency 2.488GHz clock for timing the outgoing data streams.
The MAX3831/MAX3832's demux receives 2.488Gbps serial data and the 2.488GHz clock from an external clock/data recovery device (MAX3876), converting it to four 622Mbps LVDS outputs. The MAX3831 provides a 622MHz LVDS clock output, and the MAX3832 provides a 155MHz LVDS clock output. An internal frame detector looks for a 622Mbps SDH/SONET framing pattern and rolls the demux to maintain proper channel assignment at the outputs.
These devices also include an embedded pattern generator that enables a full-speed, built-in self-test (BIST). Two different loopback modes provide system test flexibility. A TTL loss-of-frame monitor is included. The MAX3831/MAX3832 are available in 64-pin TQFP-EP (exposed paddle) packages and are specified over the upper commercial (0°C to +85°C) temperature range.
* Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.
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MAX3831
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MAX3831UCB-D
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TQFP-EP;64 pin;148.8 mm²
Outline Drawing: 21-0084 (PDF)
Land Pattern: 90-0327 (PDF)
Use pkgcode/variation: C64E-3*
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