HDLC Configuration of Framers and Transceivers - マキシム [Open results in new window]
... BITMAP, NAME, VALUE, FUNCTION. T1TCR1.2, TFDLS, 1, Source FDL data from the HDLC
controller.
T1TCR2.6, TSCL96, 0, Disable SLC-96 and D4 Fs-bit insertion. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/394 - 52k
HDLCコントローラDS31256 ... [Open results in new window]
This application note describes how to configure a single T1 port on DS31256
HDLC Controller operating in bridge
mode. The sample ...
japan.maxim-ic.com/appnotes.cfm/an_pk/2872 - 79k
HDLCコントローラDS31256 ... [Open results in new window]
This application note describes how to configure a single T1 port on DS31256
HDLC Controller operating in configuration
mode. The ...
japan.maxim-ic.com/appnotes.cfm/an_pk/2871 - 81k
Initialization Steps for the DS31256 - マキシム [Open results in new window]
... Initialization Steps for the DS31256. Abstract: The recommended initialization
sequences for DS31256 Envoy
HDLC controller before sending packet data. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/2867 - 25k
DS21354/DS21554 vs. DS2154 Single Chip Transceivers - マキシム [Open results in new window]
... 2. Additional Functionality. New Features, Data Sheet Section. HDLC controller,
15. JTAG, 17. ...
CCR6, 1Dh, Common Control Register 6. 3.2 HDLC Controller (section ...
japan.maxim-ic.com/appnotes.cfm/an_pk/361 - 27k
Examples of DS31256 Applications - マキシム [Open results in new window]
Provides some application examples of the Dallas
Semiconductor/Maxim DS31256 HDLC Controller. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/3345 - 25k
Internal Test Registers for the DS31256 - マキシム [Open results in new window]
... キーワード: hdlc controller, test registers, HDLC,
controllers. 関連製品. APP 3071: Mar 09, 2004. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/3071 - 20k
Interleaved Bus Operation - マキシム [Open results in new window]
The example application includes the DS31256 HDLC controller that can be used to
interleave multiple DS21FF4 framers
onto a PCI bus using an 8MHz interl. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/3760 - 29k
DS21352/DS21552 versus DS2152 Single Chip Transceiver ... [Open results in new window]
... 2. Additional Functionality. New Features, Data Sheet Section. HDLC controller Buffer
depth increased
from 16 to 64 bytes HDLC over DS0 functionality added, 15. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/360 - 26k
DS31256 Loopback Modes - マキシム [Open results in new window]
Provides the definition and functionality of different loop back modes
of the Dallas Semiconductor DS31256 HDLC Controller.
...
japan.maxim-ic.com/appnotes.cfm/an_pk/399 - 25k
DS31256 Gapped Clock Applications - マキシム [Open results in new window]
This application note discusses how to realize gapped clock applications with the
DS31256 HDLC Controller. ...
キーワード: gapped clock, hdlc controller, HDLC. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/392 - 26k
DS31256 PCI Bus Utilization - マキシム [Open results in new window]
... キーワード: HDLC Controller, PCI Bus Utilization, app
note 3475. 関連製品. APP 3475: Mar 23, 2005. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/3475 - 33k
DS21Q44 vs. DS21Q43A - マキシム [Open results in new window]
... Per-channel idle control, 11. HDLC controller: 64-byte buffers; Can be used on Sa
bits or DS0 channels.
15. 8Mbps interleaved PCM bus operation, 16. JTAG support ...
japan.maxim-ic.com/appnotes.cfm/an_pk/356 - 55k
DS21Q41, DS21Q43 Interfacing to the MC68MH360 QUICC32 ... [Open results in new window]
... between the DS21Q41 or DS21Q43 and the Motorola MC68MH360 (QUICC32) are shown in
Figure 1. The MC68MH360 can
be configured as an HDLC controller implementing ...
japan.maxim-ic.com/appnotes.cfm/an_pk/320 - 22k
Ethernet-over-PDHテクノロジの概要 - マキシム [Open results in new window]
... キーワード: EoPDH, EoPoS, EoP, Ethernet over PDH, EthernetオーバPDH, GFP,
HDLC, cHDLC, フレームのカプセル化, Ethernetマッピング
...
japan.maxim-ic.com/appnotes.cfm/an_pk/3849/ - 48k
DS21Q42 vs. DS21Q41B - マキシム [Open results in new window]
... HDLC controller: 64-byte buffers; Configurable for FDL or DS0 access. 14. Programmable
inband code generation
and detection, 16. Interleaved PCM bus operation, ...
japan.maxim-ic.com/appnotes.cfm/an_pk/357 - 50k
DS33Z11 ― イーサネットLANと非フレーム化T1/E1 WAN ... [Open results in new window]
... キーワード: T1/E1, WAN, LAN, Ethernet, イーサネット, HDLC, X.86, elite,
ブリッジ, T1, E1, WANブリッジ, eline, elan, tls.
関連製品. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/3411 - 33k
DS2152, DS2154, DS21x5Y, and DS2155 Interfacing to the MC68360 ... [Open results in new window]
... DS2154, DS21x5Y, or DS2155 and the Motorola MC68MH360 (QUICC32) are shown in Figure
1. The MC68MH360 can be
configured as an HDLC controller implementing ...
japan.maxim-ic.com/appnotes.cfm/an_pk/319 - 24k
DS31256 and T1/E1 Interface - マキシム [Open results in new window]
How to connect the DS31256 HDLC Controller to the DS2155, DS21Q55, DS21Q50 and DS26528. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/390 - 53k
DS2155 and DS26502 Software Comparison - マキシム [Open results in new window]
... 30, INFO7, Information Register 7. 31, H1RC, HDLC #1 Receive Control. 32, H2RC,
HDLC #2 Receive
Control. ... 90, H1TC, HDLC #1 Transmit Control. 91, H1FC, HDLC #1 FIFO ...
japan.maxim-ic.com/appnotes.cfm/an_pk/3360 - 74k
