Search Results: EDGE

1-Wire® Extended Network Standard - Maxim [Open results in new window]
... A noise glitch during the rising edge can cause the 1-Wire device to become
unsynchronized with the master. The improvements to ...
korea.maxim-ic.com/appnotes.cfm/appnote_number/3925 - 35k

The MAX2265 Is Ideal for EDGE Base-Station Pre-Driver Applications ... [Open results in new window]
... EDGE, which stands for "Enhanced Data Rates for GSM Evolution," essentially triples
the existing GSM data rate from 1-bit/symbol GMSK (gaussian minimum shift ...
korea.maxim-ic.com/appnotes.cfm/an_pk/1829 - 23k

Critical DAC Parameters for Multi-Carrier GSM/EDGE Transmitters ... [Open results in new window]
... 애플리케이션 노트 1886. Critical DAC Parameters for Multi-Carrier GSM/EDGE
Transmitters. ... DAC Dynamic Performance Requirements for GSM/EDGE. ...
korea.maxim-ic.com/appnotes.cfm/an_pk/1886 - 28k

User's Guide to the DS28DG02 - Maxim [Open results in new window]
... SPI Mode, CPOL, CPHA, Description. 0 or (0,0), 0. 0. The clock idle state is low.
Data is captured on the rising clock edge and shifted out on the falling clock ...
korea.maxim-ic.com/appnotes.cfm/an_pk/4040 - 53k

Replacing the DS1202 with the DS1302 - Maxim [Open results in new window]
... note. Software 3-Wire Read Cycle. Data on the I/O pin must be read after
the falling edge of SCLK and before the rising edge of SCLK. ...
korea.maxim-ic.com/appnotes.cfm/an_pk/118 - 20k

Inexpensive (Almost Free) Probe/Tweezers for Testing SMD ... [Open results in new window]
... The angles make a clean beveled edge on the copper and avoid rough, jagged trace
edges. Figure 4. The two rectangular spacers are soldered to one board. ...
korea.maxim-ic.com/appnotes.cfm/an_pk/4459 - 22k

DS26528 and DS26524 Transmit Pulse Control - Maxim [Open results in new window]
... Each edge may be moved in both positive and negative directions in increments
of 1/32 of TCLK. General Recommendations. Modifying ...
korea.maxim-ic.com/appnotes.cfm/an_pk/3718 - 36k

Transmit Pulse Control on the DS26518 T1/E1/J1 Transceiver - Maxim [Open results in new window]
... Each edge can be moved in both positive and negative directions in increments
of 1/32 of TCLK. ... Clock Edge (1CE), Register L1TXLAA CEA[2:0]. ...
korea.maxim-ic.com/appnotes.cfm/an_pk/4325 - 38k

Using Maxim RTCs with 3-Wire Interface - Maxim [Open results in new window]
... Data is clocked into the RTC, through the I/O pin, on the rising edges of
SCLK, and data is clocked out on the falling edge of SCLK. ...
korea.maxim-ic.com/appnotes.cfm/an_pk/619 - 36k

Remote Keyless Entry with the MAXQ3212 - Maxim [Open results in new window]
... measure the times between rising and falling signal edges, and to recognize the
synchronization preamble. The most efficient way to measure edge distances is ...
korea.maxim-ic.com/appnotes.cfm/an_pk/3765 - 27k

DS26334 and DS26324 Transmit Pulse Control - Maxim [Open results in new window]
... Each edge can be moved in both positive and negative directions in increments
of 1/32 of TCLK. General Recommendations. Modifying ...
korea.maxim-ic.com/appnotes.cfm/an_pk/3619 - 35k

Manchester Data Encoding for Radio Communications - Maxim [Open results in new window]
... can be written to not only anticipate the timing of valid edges but which can reject
further edges that occur until the next valid edge transition time. ...
korea.maxim-ic.com/appnotes.cfm/an_pk/3435 - 28k

High-Speed Pulse Generator Has Programmable Levels - Maxim [Open results in new window]
... limitation with analog comparators or advanced CMOS logic gates, which create faster
digital edges. ... and U2's COM pin connect to V_LOW, and a rising edge on Φ1 ...
korea.maxim-ic.com/appnotes.cfm/an_pk/1866 - 22k

Waking up a DS2761/DS2762 - Maxim [Open results in new window]
... There is another set of conditions that can transition the devices from Sleep Mode
into Active Mode: a rising edge of DQ, a falling edge of PS, attaching a ...
korea.maxim-ic.com/appnotes.cfm/an_pk/3225 - 31k

DS31256 Gapped Clock Applications - Maxim [Open results in new window]
... bit (LSB). Bits that are to be processed by the DS31256 are clocked in
or out on the rising or falling edge of RCn/TCn. Figure 2 ...
korea.maxim-ic.com/appnotes.cfm/an_pk/392 - 25k

Understanding the ATE SPI (Serial Peripheral Interface) - Maxim [Open results in new window]
... The basic operation of the SPI interface (Figure 1) is to fill the Shift register
with data (DIN), clocked in by either the rising or falling edge of SCLK. ...
korea.maxim-ic.com/appnotes.cfm/an_pk/4609 - 33k

Jitter Measurements for CLK Generators or Synthesizers - Maxim [Open results in new window]
... Accumulated Jitter: J AC (n). Jitter J AC (n) is the time displacement of the edges
of a clock relative to the triggering edge of the same clock. ...
korea.maxim-ic.com/appnotes.cfm/an_pk/2744 - 26k

Interfacing SPI Peripherals to the MAX7651 Processor - Maxim [Open results in new window]
... Table 1. The Four Variations CPOL. CPHA. Transfer. 0. 0. SCK rising-edge transfer.
SCK transitions in middle of bit timing. 1. 0. SCK falling-edge transfer. ...
korea.maxim-ic.com/appnotes.cfm/an_pk/802 - 30k

Determining Clock Accuracy Requirements for UART Communications ... [Open results in new window]
... A new frame is recognized by the falling edge at the beginning of the active-low
Start bit, when the signal changes from the active-high Stop bit or bus idle ...
korea.maxim-ic.com/appnotes.cfm/an_pk/2141/ - 71k