Search Results: EDGE

The MAX2265 Is Ideal for EDGE Base-Station Pre-Driver Applications ... [Open results in new window]
... EDGE, which stands for "Enhanced Data Rates for GSM Evolution," essentially triples
the existing GSM data rate from 1-bit/symbol GMSK (gaussian minimum shift ...
japan.maxim-ic.com/appnotes.cfm/an_pk/1829 - 23k

500mW PHS Transmitter Meets Transient Spectrum Requirements with ... [Open results in new window]
... 500mW PHS Transmitter Meets Transient Spectrum Requirements with Edge Control. ...
Case #2: TX gate control signal with cosine edge shape. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/1997 - 24k

DS26528およびDS26524の送信パルス波形制御 ... [Open results in new window]
... Overshoot (1) -- Register L1TXLAA WLA[4:0]; Clock Edge (1CE) -- Register L1TXLAA
CEA[2:0] (1CE) = Clock Edge transition from Overshoot to Plateau; ...
japan.maxim-ic.com/appnotes.cfm/an_pk/3718 - 38k

Replacing the DS1202 with the DS1302 - マキシム [Open results in new window]
... note. Software 3-Wire Read Cycle. Data on the I/O pin must be read after
the falling edge of SCLK and before the rising edge of SCLK. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/118 - 20k

Inexpensive (Almost Free) Probe/Tweezers for Testing SMD ... [Open results in new window]
... The angles make a clean beveled edge on the copper and avoid rough, jagged trace
edges. Figure 4. The two rectangular spacers are soldered to one board. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/4459 - 23k

Using Maxim RTCs with 3-Wire Interface - マキシム [Open results in new window]
... Data is clocked into the RTC, through the I/O pin, on the rising edges of
SCLK, and data is clocked out on the falling edge of SCLK. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/619 - 37k

High-Speed Pulse Generator Has Programmable Levels - マキシム [Open results in new window]
... limitation with analog comparators or advanced CMOS logic gates, which create faster
digital edges. ... and U2's COM pin connect to V_LOW, and a rising edge on Φ1 ...
japan.maxim-ic.com/appnotes.cfm/an_pk/1866 - 22k

Waking up a DS2761/DS2762 - マキシム [Open results in new window]
... There is another set of conditions that can transition the devices from Sleep Mode
into Active Mode: a rising edge of DQ, a falling edge of PS, attaching a ...
japan.maxim-ic.com/appnotes.cfm/an_pk/3225 - 31k

DS31256 Gapped Clock Applications - マキシム [Open results in new window]
... bit (LSB). Bits that are to be processed by the DS31256 are clocked in
or out on the rising or falling edge of RCn/TCn. Figure 2 ...
japan.maxim-ic.com/appnotes.cfm/an_pk/392 - 26k

Understanding the ATE SPI (Serial Peripheral Interface) ... [Open results in new window]
... The basic operation of the SPI interface (Figure 1) is to fill the Shift register
with data (DIN), clocked in by either the rising or falling edge of SCLK. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/4609 - 33k

Jitter Measurements for CLK Generators or Synthesizers ... [Open results in new window]
... Accumulated Jitter: J AC (n). Jitter J AC (n) is the time displacement of the edges
of a clock relative to the triggering edge of the same clock. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/2744 - 27k

Interfacing SPI Peripherals to the MAX7651 Processor ... [Open results in new window]
... Table 1. The Four Variations CPOL. CPHA. Transfer. 0. 0. SCK rising-edge transfer.
SCK transitions in middle of bit timing. 1. 0. SCK falling-edge transfer. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/802 - 30k

Determining Clock Accuracy Requirements for UART Communications ... [Open results in new window]
... A new frame is recognized by the falling edge at the beginning of the active-low
Start bit, when the signal changes from the active-high Stop bit or bus idle ...
japan.maxim-ic.com/appnotes.cfm/an_pk/2141/ - 72k

Interfacing the DS1620 with a DS5000/8051 Microcontroller ... [Open results in new window]
... A clock cycle is a sequence of a falling edge followed by a rising edge. For data
inputs, the data must be valid during the rising edge of the clock cycle. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/134 - 39k

Interfacing the DS21x5y to the TMS320C54x - マキシム [Open results in new window]
... Updated on the rising edges of RCLK when the receiveside elastic store is disabled.
Updated on the rising edge of RSYSCLK when the elastic store is enabled. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/359 - 33k

DS2148/DS21348 Hardware Mode - マキシム [Open results in new window]
... CCR2.2, HBE, Transmit HDB3.B8ZS Enable. CCR2.1, CES, Transmit Clock Edge Select.
CCR2.0, CES, Receive Clock Edge Select. ... CES, 12, I, Receive & Transmit Clock Edge ...
japan.maxim-ic.com/appnotes.cfm/an_pk/407 - 39k

Ultra-High-Speed Flash Microcontroller Software SPI - マキシム [Open results in new window]
... CKPHA changes the edge used to signal transfer of data. When ... input. With CKPHA =
1, the second edge of SPI_CLK specifies when to sample. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/3078 - 25k

LVDS Enables High-Speed Signal Distribution in 3G Basestations ... [Open results in new window]
... LVDS, low voltage, differential signaling, signalling, lvds, EIA/TIA-644, 3G, signal
distribution, clock distribution, W-CDMA, EDGE, CDMA2000, basestations. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/1058 - 31k

Design a Low-Jitter Clock for High-Speed Data Converters ... [Open results in new window]
... Edge-to ... EQ. 5 can be reduced to: The edge-to-edge timing jitter due to the noise
floor is: Because thermal noise is non-correlated, jitter is non-accumulated. ...
japan.maxim-ic.com/appnotes.cfm/an_pk/800 - 44k