Power-supply noise can degrade clock jitter and affect the performance of every component in the signal path. Supply noise problems are usually found late in the design cycle and can necessitate expensive redesigns and cause painful schedule delays.
Maxim clock generator ICs have the best power-supply noise rejection in the industry and minimize the risk of project delays due to supply noise problems.
Power-supply noise problems can be solved in two ways:
Minimize noise sources: Choose power supplies with less voltage noise and minimize inductance in power-supply decoupling loops
Make the clock less sensitive to noise: Choosing a clock generator with excellent PSNR minimizes design risk by ensuring that system performance equals EV kit results so you don't get any surprises on power-on.
Maxim's clock generators achieve industry leading PSNR of -50dBc or better at 100kHz for 40mVP-P power-supply noise. More importantly, Maxim delivers good PSNR for a broad range of frequencies so you don't get surprises from unusual spurs.
Example: MAX3624 PSNR for 312.5MHz Output with 40mVP-P Power-Supply Noise
Maxim employs three main design techniques to deliver excellent PSNR:
Differential circuits: Differential circuits attenuate common-mode effects such as supply noise.
Bipolar transistors: Our process allows Maxim to achieve far better common-mode cancellation than MOS circuits. Channel-length modulation makes MOS transistors 5x more sensitive to supply effects than bipolar transistors. Further improving PSNR, superior matching of bipolar transistors minimizes common-mode-to-differential conversion.
Local regulation: By regulating supply voltages internally, Maxim clock generators shield the VCO, XO, and other sensitive circuits from power-supply noise. On-chip regulators attenuate power supply noise before it affects jitter performance.
To ensure success, Maxim designers simulate PSNR over process, supply, and voltage corners, and confirm results with measurements on the bench.
