Power-supply noise can degrade clock jitter and affect the performance of every component in the signal path. Supply noise problems are usually found late in the design cycle and can necessitate expensive redesigns and cause painful schedule delays.
Maxim clock generator ICs have the best power-supply noise rejection in the industry and minimize the risk of project delays due to supply noise problems.
Power-supply noise injected into the clock is distributed to every component in the system. PSNR can increase jitter, degrade BER, and cause dropped packets.
The best assessment of overall clock performance is time interval error (TIE), which combines random jitter from the clock generator with deterministic jitter caused by power-supply noise. TIE in ps peak-to-peak can be computed as follows:
TIE = 14 × RJ + DJ
where DJ is the deterministic jitter caused by power-supply noise. DJ can be computed as follows:
DJ = ( 2 × 10(PSNR/20)/(π × fc)) × 1012pspeak-to-peak
Applying this equation to a 10-Gigabit Ethernet application requiring a 156.25MHz clock and operating from a power supply having 40mVP-P noise at 100kHz, Maxim clock generators achieve 10x better TIE performance than our leading competitor.
