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Maxim >
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Clock Generation and Distribution
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Small Clock Tree for a Single-Board Ethernet Switch
A stackable or "pizza-box" Ethernet switch is built on a single PCB. The clock tree must drive PHY ICs as well as the switch.
Consider a system that requires the following low-jitter clocks:
- 3 LVCMOS at 125MHz
- 4 LVDS at 125MHz
- 1 LVDS at 156.25MHz
This clock tree can be implemented using either:
- 2 oscillator modules and 2 fanout buffers or
- 1 MAX3629 and a 25MHz crystal
The Maxim solution is 35% lower power and 70% smaller.
Clock Tree Implemented with Oscillator Modules and Fanout Buffers
| Component |
Power Dissipation (mW) |
Board Area (mm²) |
| Typical |
Maximum |
Package Body |
Leadframe |
Including Routing |
| 125MHz XO |
198 |
353 |
5x7 |
5x7 |
11x13 |
| 156.25MHz XO |
198 |
353 |
5x7 |
5x7 |
11x13 |
| 1:4 LVDS fanout |
142 |
216 |
4.4x5 |
6.4x5 |
12.4x11 |
| 1:4 LVCMOS fanout |
231 |
425 |
3x5 |
4x5 |
10x11 |
| TOTAL |
769 |
1347 |
107 |
122 |
532.4 |
Clock Tree Implemented with MAX3629 Clock Generator IC
| Component |
Power Dissipation (mW) |
Board Area (mm²) |
| Typical |
Maximum |
Package Body |
Leadframe |
Including Routing |
| 25MHz XTAL |
0 |
0 |
2x1.6 |
2x1.6 |
8x7.6 |
| MAX3629 |
568 |
806 |
5x5 |
5x5 |
11x11 |
| TOTAL |
568 |
806 |
28.2 |
28.2 |
181.2 |
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