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Maxim >
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Clock Generation and Distribution
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Large Clock Tree for an Ethernet Line Card
An Ethernet line card may require numerous clocks of multiple frequencies to support ports, classification, packet processing, forwarding, security, and various other sophisticated features.
Consider a line card that requires the following low-jitter clocks:
- 4 LVPECL at 312.5MHz
- 5 LVPECL at 250MHz
- 4 LVDS at 156.25MHz
- 12 LVPECL at 125MHz
- 1 LVCMOS at 125MHz
- 3 LVPECL at 62.5MHz
This clock tree can be implemented using either:
The Maxim solution is 40% lower power and 50% smaller.
Clock Tree Implemented with Oscillator Modules and Fanout Buffers
| Component |
Power Dissipation (mW) |
Board Area (mm²) |
| Typical |
Maximum |
Package Body |
Leadframe |
Including Routing |
| 312.5MHz XO |
198 |
353 |
5x7 |
5x7 |
11x13 |
| 250MHz XO |
198 |
353 |
5x7 |
5x7 |
11x13 |
| 156.25MHz XO |
198 |
353 |
5x7 |
5x7 |
11x13 |
| 125MHz XO |
198 |
353 |
5x7 |
5x7 |
11x13 |
| 62.5MHz XO |
198 |
353 |
5x7 |
5x7 |
11x13 |
| 1:4 LVPECL |
66 |
90 |
6.5x4.4 |
6.5x6.4 |
12.5x12.4 |
| 1:5 LVPECL |
66 |
90 |
6.5x4.4 |
6.5x6.4 |
12.5x12.4 |
| 1:4 LVDS |
142 |
216 |
4.4x5 |
6.4x5 |
12.4x11 |
| 1:15 LVPECL |
218 |
468 |
10x10 |
12x12 |
18x18 |
| LVPECL–LVCMOS |
13.9 |
21.6 |
8.65x3.9 |
8.65x6 |
14.65x12 |
| 1:3 LVPECL |
66 |
90 |
6.5x4.4 |
6.5x6.4 |
12.5x12.4 |
| TOTAL |
1561.9 |
2740.6 |
416.5 |
527.7 |
1816.2 |
Clock Tree Implemented with Maxim Clock Generator ICs
| Component |
Power Dissipation (mW) |
Board Area (mm²) |
| Typical |
Maximum |
Package Body |
Leadframe |
Including Routing |
| 25MHz XTAL |
0 |
0 |
2x1.6 |
2x1.6 |
8x7.6 |
| MAX3679 |
254 |
360 |
5x5 |
5x5 |
11x11 |
| MAX3671 |
396 |
594 |
8x8 |
8x8 |
14x14 |
| MAX9169 |
142 |
216 |
4.4x5 |
6.4x5 |
12.4x11 |
| MAX9322 |
218 |
468 |
10x10 |
12x12 |
18x18 |
| TOTAL |
1010 |
1638 |
214.2 |
268.2 |
838.2 |
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