Industry's First SONET/SDH Timing Card on a Chip

Key Features

• Complete Central Timing and Synchronization System Saves Design Time, Board Space, and Cost
• Includes Two Multiprotocol BITS/SSU Transceivers, 14 Input Clocks, 11 Output Clocks, and a Synchronization Subsystem Compliant with Stratum 3/3E Requirements
• Eliminates Complex Design Issues Such as Transfer Functions, Loop Equations, and DSP Algorithm Development