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DSSHA1

Memory-Mapped SHA-1 Coprocessor

Securely Offloads SHA-1 Computation to FPGA or ASIC

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Status Explanations for product status codes

Part Number Status Explanation
DSSHA1 This product is Not Recommended for New Designs.Newer versions exist. Contact factory for latest version. 

Description

The DSSHA1 coprocessor with 64-Byte RAM is a synthesizable register transfer level (RTL) implementation of the FIPS 180-3 Secure Hash Algorithm (SHA-1), eliminating the need to develop software to perform the complex SHA-1 computation required for authenticating SHA-1 devices. The DSSHA1 can compute SHA-1 message authentication codes (MACs) for use with Maxim SHA-1 devices, such as the DS1963S, DS1961S, DS28E10, DS28E02, DS2460, DS28CN01, and DS28E01-100. The device can output the 20-byte MAC result from registers required for comparison against SHA-1 slave devices. When incorporated into a design, DSSHA1 also provides an offloading function, relieving a microcontroller of performing the SHA-1 computation.
 

Data Sheet

Download this datasheet in PDF formatDownload Rev 0 (PDF, 244kB)
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Key Features

  • SHA-1 Computations Within 670 Clock Cycles (13.4µs at a Typical Frequency of 50MHz)
  • Area Estimate is 102,256µm² in TSMC CL018G (0.18µm Generic Process)
  • Dedicated Hardware-Accelerated SHA-1 Engine for Generating MACs
  • 64-Byte RAM for Message Input
  • Five 32-Bit Registers to Read the MAC Result
  • Available in Synthesizable Verilog®
  • Made as a Low-Level Module to be Instantiated by a Top-Level Module
  • Includes Test Bench
 

Applications/Uses

  • Identification and authentication of consumables
  • Printer Cartridge
  • Reference Design License Management
  • Secure Feature Control of Systems
  • Sensor/Accessory Authentication and Calibration
  • System Intellectual Property Protection
   

Diagram

DSSHA1: Typical Operating Circuit
Typical Operating Circuit

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Document Ref.: 19-5870 Rev 0; 2011-05-31
This page last modified: 2011-05-31




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