MAX3639

Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs

Clock Generator with Subpicosecond Jitter Replaces Expensive Crystal Oscillators

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Status Explanations for product status codes

Active: In Production.

Description

The MAX3639 is a highly flexible, precision phase-locked loop (PLL) clock generator optimized for the next generation of network equipment that demands low-jitter clock generation and distribution for robust high-speed data transmission. The device features subpicosecond jitter generation, excellent power-supply noise rejection, and pin-programmable LVDS/LVPECL output interfaces. The MAX3639 provides nine differential outputs and one LVCMOS output, divided into three banks. The frequency and output interface of each output bank can be individually programmed, making this device an ideal replacement for multiple crystal oscillators and clock distribution ICs on a system board, saving cost and space.

This 3.3V IC is available in a 7mm x 7mm, 48-pin TQFN package and operates from -40°C to +85°C.
 

Data Sheet

Download this datasheet in PDF formatDownload Rev 0 (PDF, 2.9MB)
Send this datasheet to any email addressE-Mail
An evaluation kit is available: MAX3639EVKIT

Key Features

  • Inputs
    • Crystal Interface: 18MHz to 33.5MHz
    • LVCMOS Input: 15MHz to 160MHz
    • Differential Input: 15MHz to 350MHz
  • Outputs
    • LVCMOS Output: Up to 160MHz
    • LVPECL/LVDS Outputs: Up to 800MHz
  • Three Individual Output Banks
    • Pin-Programmable Dividers
    • Pin-Programmable Output Interface
  • Wide VCO Tuning Range (3.60GHz to 4.025GHz)
  • Low Phase Jitter
    • 0.34psRMS (12kHz to 20MHz)
    • 0.14psRMS (1.875MHz to 20MHz)
  • Excellent Power-Supply Noise Rejection
  • -40°C to +85°C Operating Temperature Range
  • +3.3V Supply
 

Applications/Uses

  • Ethernet Switch/Router
  • Fibre Channel SAN
  • PCIe®, Network Processors
  • SONET/SDH Line Cards
  • Wireless Base Station
   

Key Specifications:

Clock Generators
Part Number Applications fIN
(MHz)
fIN
(MHz)
fOUT
(MHz)
fOUT
(MHz)
Output Levels Out-
puts
PLLs Program-
mability
Output Jitter
(ps)
VSUPPLY
(V)
Package/Pins Budgetary Price
min max min max RMS See Notes
MAX3639 
3G Wireless Base Stations
Ethernet
Fibre Channel
SONET/SDH
15 350 15 800
LVCMOS
LVDS
LVPECL
10 1 Pin 0.14 3.3
TQFN/48
$8.78 @1k
See All Clock Generators (34)
Pricing Notes:
This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific prices and delivery, please see the price and availability page or contact an authorized distributor.


Diagram

MAX3639: Functional Diagram
Functional Diagram

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Information Index

Document Ref.: 19-4911 Rev 0; 2009-10-15
This page last modified: 2010-03-01




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