Status
Active: In Production.
Description
The MAX66140 combines 1024 bits of user EEPROM with secure hash algorithm (SHA-1) challenge-and-response authentication (ISO/IEC 10118-3 SHA-1), a 64-bit unique identifier (UID), one 64-bit secret, and a 13.56MHz ISO 15693 RF interface in a single chip. The memory is organized as 16 blocks of 8 bytes plus three more blocks—one for the secret and two for data and control registers. Except for the secret, each block has a user-readable write-cycle counter. Four adjacent user EEPROM blocks form a memory page (pages 0 to 3). The integrated SHA-1 engine provides a Message Authentication Code (MAC) using data from the EEPROM of the device and the 64-bit secret to guarantee secure, symmetric authentication for both reading and writing to the device. Memory protection features are write protection and EPROM emulation, which the user can set for each individual memory page. Page 3 can also be read protected for enhanced authentication strength. The MAX66140 supports all ISO 15693-defined data rates, modulation indices, subcarrier modes, the selected state, application family identifier (AFI), data storage format identifier (DSFID), and the Option_flag bit for read operations. Memory write access (except for AFI, DSFID, and the corresponding lock bytes) is accomplished through custom commands using a write buffer with readback and copy-to-memory function.
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