Status
Active: In Production.
Description
The MAX66040 combines 1024 bits of user EEPROM with secure hash algorithm (SHA-1) challenge-and-response authentication (ISO/IEC 10118-3 SHA-1), a 64-bit unique identifier (UID), one 64-bit secret, and a 13.56MHz RF interface (ISO/IEC 14443 Type B, Parts 2-4) in a single chip. The memory is organized as 16 blocks of 8 bytes plus three more blocks, one for the secret and two for data and control registers. Except for the secret, each block has a user-readable write-cycle counter. Four adjacent user EEPROM blocks form a memory page (pages 0 to 3). The integrated SHA-1 engine provides a message authentication code (MAC) using data from the EEPROM of the device and the 64-
bit secret to guarantee secure, symmetric authentication for both reading and writing to the device. Memory protection features are write protection and EPROM emulation, which the user can set for each individual memory page. Page 3 can also be read-protected for enhanced authentication strength. Memory access is accomplished through the block transmission protocol (ISO/IEC 14443-4), where requests and responses are exchanged through I-blocks once a device is in the ACTIVE state. The data rate can be as high as 847.5kbps. The reader must support a frame size of 26 bytes. The device supports an application family identifier (AFI) and a card identifier (CID). ISO/IEC 14443 functions not supported are chaining, frame-waiting time extension, and power indication.
|
|
Data Sheet
|
Download
