MAX3624

Low-Jitter, Precision Clock Generator with Four Outputs

0.36ps Jitter and Excellent Power-Supply Noise Rejection

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Status Explanations for product status codes

All versions are Not Recommended for New Designs. See Ordering Information for recommended replacements.

Description

The MAX3624 is a low-jitter precision clock generator optimized for networking applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) clock multiplier to generate high-frequency clock outputs for Ethernet, Fibre Channel, SONET/SDH, and other networking applications.

Maxim's proprietary PLL design features ultra-low jitter (0.36psRMS) and excellent power-supply noise rejection, minimizing design risk for network equipment.

The MAX3624 has three LVPECL outputs and one LVCMOS output. Selectable output dividers and a selectable feedback divider allow a range of output frequencies.
 

Data Sheet

Download this datasheet in PDF formatDownload Rev 01 (PDF, 428kB)
Send this datasheet to any email addressE-Mail
An evaluation kit is available: MAX3624EVKIT

Key Features

  • Crystal Oscillator Interface: 19.375MHz to 27MHz
  • CMOS Input: 19MHz to 40.5MHz
  • Output Frequencies
    • Ethernet: 62.5MHz, 125MHz, 156.25MHz, 312.5MHz
    • Fibre Channel: 106.25MHz, 159.375MHz, 212.5MHz, 318.5MHz
    • SONET/SDH: 77.76MHz, 155.52MHz, 311.04MHz
  • Low Jitter
    • 0.14psRMS (1.875MHz to 20MHz)
    • 0.36psRMS (12kHz to 20MHz)
  • Excellent Power-Supply Noise Rejection
  • No External Loop Filter Capacitor Required
 

Applications/Uses

  • Ethernet Networking Equipment
  • Fibre Channel Storage Area Network
  • SONET/SDH Network
   

Diagram

MAX3624: Block Diagram
Block Diagram

More Information

New Product Press Release 2008-01-14 ]

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Information Index

Document Ref.: 19-0977 Rev 01; 2007-11-29
This page last modified: 2009-08-31




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