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DS3104
Line Card Timing IC with Synchronous Ethernet Support
SONET/SDH Line Card IC Has Full Synchronous Ethernet Support
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Status
Active: In Production.
Description
The DS3104-SE is a low-cost, feature-rich timing IC for line cards with Synchronous Gigabit Ethernet (GbE), 10-Gigabit Ethernet (10GbE), and Fast Ethernet ports. ITU-T recommendation G.8261 (formerly G.pactiming) specifies that network synchronization can be carried over packet links by synchronizing the bit clock of the physical layer as is currently done on SONET/SDH links. The DS3104-SE enables synchronization in Ethernet line cards in both the transmit and receive directions.
In the transmit direction, the device accepts traditional SONET/SDH system clocks such as 19.44MHz from redundant system timing cards and synthesizes
frequency-locked xMII clock rates, such as the 125MHz GTX_CLK for GbE GMIIs. Each Ethernet PHY then synthesizes a transmit bit clock that is frequency-locked to the xMII clock, and thus to the system clock and network clock. In the receive direction, each PHY divides down the recovered bit clock to produce the receive xMII clock. The DS3104-SE accepts the xMII clock from any of several Ethernet ports and forwards a frequency-locked system clock, such as 19.44MHz, to the system timing cards. SONET/SDH ports are also supported.
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Data Sheet
Errata DS3104 3104A1.pdfErrata DS3104 3104A2.pdf
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An evaluation kit is available: DS3104DK
Key Features
- Timing Card to Line Card Path
- Two Input Clocks from Master and Slave Timing Cards (LVDS/LVPECL or CMOS/TTL)
- Optional Frame-Sync Inputs and Outputs
- Continuous Input Clock Quality Monitoring
- Hitless Reference Switching, Automatic or Manual
- Holdover on Loss of All Inputs
- Programmable PLL Bandwidth, 0.1Hz to 400Hz
- Frequency Conversion Between SONET/SDH Rates and Ethernet MII/GMII/XGMII Rates
- Up to 7 Output Clocks: 3 CMOS/TTL (≤ 125MHz), 2 LVDS/LVPECL (≤ 312.50MHz), and 2 Dual CMOS/TTL and LVDS/LVPECL
- Line Card to Timing Card Path
- Up to 8 Input Clocks: 4 CMOS/TTL (≤ 125MHz) and 4 LVDS/LVPECL/CMOS/TTL (≤ 156.25MHz)
- Hitless Reference Switching, Automatic or Manual
- Frequency Conversion Between Ethernet MII/GMII/XGMII and SONET/SDH Rates
- Two Output Clocks to Master and Slave Timing Cards (CMOS/TTL or LVDS/LVPECL)
- General
- Suitable Line Card IC for Stratum 3/3E/4, SMC, SEC
- Numerous Input Clock Frequencies Supported
- Ethernet xMII: 2.5, 25, 125, 156.25MHz
- SONET/SDH: 6.48, N x 19.44, N x 51.84MHz
- PDH: N x DS1, N x E1, N x DS2, DS3, E3
- Frame Sync: 2kHz, 4kHz, 8kHz
- Custom: Any Multiple of 2kHz Up to 131.072MHz, Any Multiple of 8kHz Up to 155.52MHz
- Numerous Output Clock Frequencies Supported
- Ethernet xMII: 2.5, 25, 125, 156.25, 312.5MHz
- SONET/SDH: 6.48, N x 19.44, N x 51.84MHz
- PDH: N x DS1, N x E1, N x DS2, DS3, E3
- Other: 10, 10.24, 13, 30.72MHz
- Frame Sync: 2kHz, 8kHz
- Custom Clock Rates: Any Multiple of 2kHz Up to 77.76MHz, Any Multiple of 8kHz Up to 311.04MHz, Any Multiple of 10kHz Up to 388.79MHz
- Internal Compensation for Master Clock Oscillator
- SPI™ Processor Interface
- 1.8V Operation with 2.5V/3.3V I/O (5V Tolerant)
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Applications/Uses
- Line Cards with Any Mix of Synchronous Ethernet and SONET/SDH Ports in WAN Equipment Including MSPPs, Ethernet Switches, Routers, DSLAMs, and Wireless Base Stations
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Key Specifications:
| Timing Card and Line Card ICs |
| Part Number |
Indep. DPLLs |
Input Clocks |
Diff. Input Clocks |
Output Clocks |
Diff. Output Clocks |
fCLKIN |
fCLKOUT |
DPLL BW (Hz) |
DPLL BW (Hz) |
Smallest Available Pckg. (mm2) |
Budgetary Price |
| min |
max |
max w/pins |
See Notes |
| DS3104 |
2 |
8 |
4 |
7 |
4 |
| 2kHz and 4kHz | | 25.00MHz | | 125.00MHz | | 156.25MHz | | 312.5MHz | | N x 19.44MHz | | N x 2kHz up to 131.072MHz | | N x 8kHz up to 155.52MHz | | N x DS1 | | N x E1 |
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| 2kHz | | 6.48MHz | | 8kHz | | 25.00MHz | | 51.84MHz | | 62.5MHz | | 125.00MHz | | 155.52MHz | | 156.25MHz | | 311.04MHz | | 312.5MHz | | DS3 | | E3 | | N x 10kHz up to 388.79MHz | | N x 19.44MHz | | N x 2kHz up to 77.76MHz | | N x 8kHz up to 311.04MHz | | N x DS1 | | N x DS2 | | N x E1 |
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0.1 |
400 |
100 |
$34.61 @1k |
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See All Timing Card and Line Card ICs (12)
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Pricing Notes:
This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific prices and delivery, please see the price and availability page or contact an authorized distributor.
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Diagram
Block Diagram
Application Notes
Product Guides
Reliability Reports
Software/Models
Ordering Information
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Part Number
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Free Sample |
Buy |
Status
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Package:
TYPE PINS FOOTPRINT
DRAWING CODE/VAR *
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Temp |
RoHS/Lead-Free? Materials Analysis
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| DS3104GN
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Active |
CSBGA;81 pin;100 mm²
Outline Drawing:21-0360 (PDF)
Land Pattern: 90-0293 (PDF)
Use pkgcode/variation: X81-1*
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-40°C to +85°C
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RoHS/Lead-Free: No
Materials Analysis |
| DS3104GN+
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Active |
CSBGA;81 pin;100 mm²
Outline Drawing:21-0360 (PDF)
Land Pattern: 90-0293 (PDF)
Use pkgcode/variation: X81+1*
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-40°C to +85°C
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RoHS/Lead-Free: Lead Free
Materials Analysis |
| DS3104GN-W
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Active |
CSBGA;81 pin;100 mm²
Outline Drawing:21-0360 (PDF)
Land Pattern: 90-0293 (PDF)
Use pkgcode/variation: X81-1*
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-40°C to +85°C
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RoHS/Lead-Free: No
Materials Analysis |
Notes:
- Other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales.
- Didn't Find What You Need? Ask our applications engineers. Expert assistance in finding parts, usually within one business day.
- Part number suffixes: T or T&R = tape and reel; + = RoHS/lead-free; # = RoHS/lead-exempt; -D = drypack; -U/+U on DS parts = cut tape. More: See Full Data Sheet or Maxim Product Naming Conventions.
- * Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.
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Information Index
Document Ref.: 19-4627
Rev 7;
2010-09-08
This page last modified: 2010-09-08
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