DS3101

Stratum 2/3E/3 Timing Card IC

SONET/SDH Stratum 3/3E Compliant Timing Card IC

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Status Explanations for product status codes

Active: In Production.

Description

When paired with an external TCXO or OCXO, the DS3101 is a highly integrated central timing and synchronization solution for SONET/SDH network elements. With 14 input clocks, the device directly accepts both line timing from a large number of line cards and external timing from external DS1/E1 BITS transceivers. All input clocks are continuously monitored for frequency accuracy and activity. Any two of the input clocks can be selected as the references for the two core DPLLs. The T0 DPLL complies with the Stratum 2, 3E, 3, 4E and 4 requirements of GR1244, GR-253, G.812 Types I–IV, G.813 and G.8262. From the output of the core DPLLs, a wide variety of output clock frequencies and frame pulses can be produced simultaneously on the 11 output clock pins. Two DS3101 devices can be configured in a master/slave arrangement for timing card equipment protection.

The DS3101 registers and I/O pins are backward compatible with Semtech's ACS8520 and ACS8530 timing card ICs. The DS3101 is functionally equivalent to a DS3100 without integrated BITS transceivers.
 

Data Sheet

Download this datasheet in PDF formatDownload Rev 3 (PDF, 672kB)
Send this datasheet to any email addressE-Mail

Errata DS3101 3101A1.pdf
Errata DS3101 3101A2.pdf

Key Features

  • Synchronization Subsystem for Stratum 2, 3E, 3, 4E and 4 plus SMC, SEC and EEC
    • Meets Requirements of GR-1244 Stratum 2–4, GR-253, G.812 Types I–IV, G.813 and G.8262
    • Stratum 2, 3E or 3 Holdover Accuracy with Suitable External Oscillator
    • Programmable Bandwidth, 0.5mHz to 70Hz
    • Hitless Reference Switching on Loss of Input
    • Phase Build-Out and Transient Absorption
    • Locks To and Generates 125MHz for Gigabit Synchronous Ethernet per ITU-T G.8261
  • 14 Input Clocks
    • 10 CMOS/TTL Inputs Accept 2kHz, 4kHz, and Any Multiple of 8kHz Up to 125MHz
    • Two LVDS/LVPECL/CMOS/TTL Inputs Accept Nx8kHz Up to 125MHz Plus 155.52MHz
    • Two 64kHz Composite Clock Receivers
    • Continuous Input Clock Quality Monitoring
    • Separate 2/4/8kHz Frame Sync Input
  • 11 Output Clocks
    • Five CMOS/TTL Outputs Drive Any Internally Produced Clock Up to 77.76MHz
    • Two LVDS Outputs Each Drive Any Internally Produced Clock Up to 311.04MHz
    • One 64kHz Composite Clock Transmitter
    • One 1.544MHz/2.048MHz Output Clock
    • Two Sync Pulses: 8kHz and 2kHz
    • Output Clock Rates Include 2kHz, 8kHz, NxDS1, NxDS2, DS3, NxE1, E3, 6.48MHz, 19.44MHz, 38.88 MHz, 51.84MHz, 62.5MHz, 77.76MHz, 125MHz, 155.52MHz, 311.04MHz
  • Internal Compensation for Master Clock Oscillator Frequency Accuracy
  • Processor Interface: 8-Bit Parallel or SPI Serial
  • 1.8V Operation with 3.3V I/O (5V Tolerant)
 

Applications/Uses

  • Digital Cross-Connects
  • DSLAMs
  • Service Provider Routers
  • SONET/SDH ADMs, MSPPs, and MSSPs
   

Key Specifications:

Timing Card and Line Card ICs
Part Number Indep. DPLLs Input Clocks Diff. Input Clocks Output Clocks Diff. Output Clocks fCLKIN fCLKOUT DPLL BW
(Hz)
DPLL BW
(Hz)
Smallest Available Pckg.
(mm2)
Budgetary Price
min max max w/pins See Notes
DS3101  2 14 2 11 3
2kHz and 4kHz
N x 19.44MHz
N x 8kHz up to 155.52MHz
N x DS1
N x E1
2kHz
6.48MHz
8kHz
25.00MHz
51.84MHz
62.5MHz
125.00MHz
155.52MHz
311.04MHz
DS3
E3
N x 19.44MHz
N x DS1
N x DS2
N x E1
0.0005 70 289 $60.80 @1k
See All Timing Card and Line Card ICs (12)
Pricing Notes:
This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific prices and delivery, please see the price and availability page or contact an authorized distributor.


Diagram

DS3101: Functional Diagram
Functional Diagram

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Description
Key Features
Applications/Uses
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Notes and Comments
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Document Ref.: 19-4596 Rev 3; 2009-05-12
This page last modified: 2009-05-13




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