2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier

All versions are No Longer Available. See Ordering Information for recommended replacements.

The MAX3874 is a compact, dual-rate clock and data recovery with limiting amplifier for OC-48 and OC-48 with FEC SONET/SDH applications. Without using an external reference clock, the fully integrated phaselocked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input. The input data is then retimed by this recovered clock, providing a clean data output. An additional serial input (SLBI±) is available for system-loopback diagnostic testing. Alternatively, this input can be connected to a reference clock to maintain a valid clock output in the absence of data transitions. The device also includes a loss-of-lock (LOL-bar) output.

The MAX3874 contains a vertical threshold control to compensate for optical noise due to EDFAs in DWDM transmission systems. The recovered data and clock outputs are CML with on-chip 50Ω back termination on each line. Its jitter performance exceeds all SONET/SDH specifications. The MAX3874A is the MAX3874 with a voltage-controlled oscillator (VCO) centered at 2.0212GHz.

The MAX3874 operates from a single +3.3V supply and typically consumes 580mW. It is available in a 5mm x 5mm 32-pin QFN with exposed pad package and operates over the -40°C to +85°C temperature range.

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