DS31256 256-Channel, High-Throughput HDLC Controller 256-Channel HDLC Controller Capable of Handling Up to 60 T1 or 64 E1 Data Streams or Two T3 Data Streams

Overview

Technical Documents

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Status Part Number Status DS31256 This product is Not Recommended for New Designs.

Data Sheet Download Rev 4 (PDF, 1.2MB) E-Mail Errata DS31256 31256B2.pdf Errata DS31256 31256A2.pdf

Application Notes

Application Note 390		DS31256 and T1/E1 Interface
Application Note 392		DS31256 Gapped Clock Applications
Application Note 399		DS31256 Loopback Modes
Application Note 2867		Initialization Steps for the DS31256
Application Note 2871		DS31256 HDLC Controller Step-by-Step Configuration—Configuration Mode
Application Note 2872		DS31256 HDLC Controller Step-by-Step Configuration—Bridge Mode
Application Note 3071		Internal Test Registers for the DS31256
Application Note 3259		DS31256 Envoy—Example Code for Registers Dump
Application Note 3344		DS31256 -- T3/E3 MUX/DS3112 Hardware Connections
Application Note 3345		Examples of DS31256 Applications
Application Note 3347		DS31256 Unchannelized T3/E3/HSSI/VDSL Port Configuration for Bridge Mode Applications
Application Note 3475		DS31256 PCI Bus Utilization
Application Note 3760		Interleaved Bus Operation
Application Note 3818		Enabling Fractional-T1 (FT1) Loopback Detection on the DS31256

Product Guides

Communications (PDF)

Reliability Reports

Reliability Report:

DS31256.pdf

Software/Models

DS31256 BSDL Model

DS31256 Cadence Concept Symbol

DS31256 IBIS Model

DS31256 Logical Symbol-XML Format

DS31256_A2 BSDL Model

DS31256_B1 BSDL Model

DS31256_B2 BSDL Model

DS31256_B2V BSDL Model

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Information Index

Rev 4; 2006-01-27
This page last modified: 2009-10-13