DS31256

256-Channel, High-Throughput HDLC Controller

256-Channel HDLC Controller Capable of Handling Up to 60 T1 or 64 E1 Data Streams or Two T3 Data Streams

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Status Explanations for product status codes

Part Number Status
DS31256 This product is Not Recommended for New Designs.

Description

The DS31256 is a 256-channel HDLC controller that can handle up to 60 T1 or 64 E1 data streams or two T3 data streams. Each of the 16 physical ports can handle one, two, or four T1 or E1 data streams. The DS31256 is composed of the following blocks: Layer 1, HDLC processing, FIFO, DMA, PCI bus, and local bus.

There are 16 HDLC engines (one for each port) that are each capable of operating at speeds up to 8.192Mbps in channelized mode and up to 10Mbps in unchannelized mode. The DS31256 also has three fast HDLC engines that only reside on Ports 0, 1, and 2. They are capable of operating at speeds up to 52Mbps.
 

Data Sheet

Download this datasheet in PDF formatDownload Rev 4 (PDF, 1.2MB)
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Errata DS31256 31256B2.pdf
Errata DS31256 31256A2.pdf

Key Features

  • 256 Independent, Bidirectional HDLC Channels
  • Up to 132Mbps Full-Duplex Throughput
  • Supports Up to 60 T1 or 64 E1 Data Streams
  • 16 Physical Ports (16 Tx and 16 Rx) That Can Be Independently Configured for Channelized or Unchannelized Operation
  • Three Fast (52Mbps) Ports; Other Ports Capable of Speeds Up to 10Mbps (Unchannelized)
  • Channelized Ports Can Each Handle One, Two, or Four T1 or E1 Lines
  • Per-Channel DS0 Loopbacks in Both Directions
  • Over-Subscription at the Port Level
  • Transparent Mode Supported
  • On-Board Bit Error-Rate Tester (BERT) with Automatic Error Insertion Capability
  • BERT Function Can Be Assigned to Any HDLC Channel or Any Port
  • Large 16kB FIFO in Both Receive and Transmit Directions
  • Efficient Scatter/Gather DMA Maximizes Memory Efficiency
  • Receive Data Packets are Time-Stamped
  • Transmit Packet Priority Setting
  • V.54 Loopback Code Detector
  • Local Bus Allows for PCI Bridging or Local Access
  • Intel or Motorola Bus Signals Supported
  • Backward Compatibility with DS3134
  • 33MHz 32-Bit PCI (V2.1) Interface
  • 3.3V Low-Power CMOS with 5V Tolerant I/O
  • JTAG Support IEEE 1149.1
  • 256-Pin Plastic BGA (27mm x 27mm)


Features continued on page 6 of the PDF data sheet.
 

Applications/Uses

  • Channelized and Clear Channel (Unchannelized) T1/E1 and T3/E3
  • High-Density Frame-Relay Access
  • High-Density V.35
  • Routers with Multilink PPP Support
  • SONET/SDH EOC/ECC Termination
  • Triple HSSI
  • xDSL Access Multiplexers (DSLAMs)
   

Diagram

DS31256: Block Diagram
Block Diagram

Application Notes

Application Note 390   DS31256 and T1/E1 Interface
Application Note 392   DS31256 Gapped Clock Applications
Application Note 399   DS31256 Loopback Modes
Application Note 2867   Initialization Steps for the DS31256
Application Note 2871   DS31256 HDLC Controller Step-by-Step Configuration—Configuration Mode
Application Note 2872   DS31256 HDLC Controller Step-by-Step Configuration—Bridge Mode
Application Note 3071   Internal Test Registers for the DS31256
Application Note 3259   DS31256 Envoy—Example Code for Registers Dump
Application Note 3344   DS31256 -- T3/E3 MUX/DS3112 Hardware Connections
Application Note 3345   Examples of DS31256 Applications
Application Note 3347   DS31256 Unchannelized T3/E3/HSSI/VDSL Port Configuration for Bridge Mode Applications
Application Note 3475   DS31256 PCI Bus Utilization
Application Note 3760   Interleaved Bus Operation
Application Note 3818   Enabling Fractional-T1 (FT1) Loopback Detection on the DS31256

Product Guides

Communications (PDF)

Reliability Reports

Reliability Report: DS31256.pdf

Software/Models

DS31256 BSDL Model
DS31256 Cadence Concept Symbol
DS31256 IBIS Model
DS31256 Logical Symbol-XML Format
DS31256_A2 BSDL Model
DS31256_B1 BSDL Model
DS31256_B2 BSDL Model
DS31256_B2V BSDL Model

Ordering Information

Filters: Part Number: Package: Temperature: Tape and Reel Sample
Part Number Free
Sample
Buy Status Explanations for product status codes Package:
TYPE PINS FOOTPRINT
DRAWING  CODE/VAR *
Temp RoHS/Lead-Free?
Materials Analysis
DS31256    
NRND PBGA;256 pin;729 mm²
Outline Drawing:21-0307 (PDF)
Land Pattern: 90-0267 (PDF)
Use pkgcode/variation: V256-2*
0°C to +70°C RoHS/Lead-Free: No
Materials Analysis
DS31256+     N/A NRND BGA;

Land Pattern: Not Available

0°C to +70°C See data sheet
DS31256B    
NRND PBGA;256 pin;729 mm²
Outline Drawing:21-0307 (PDF)
Land Pattern: 90-0267 (PDF)
Use pkgcode/variation: V256-2*
0°C to +70°C RoHS/Lead-Free: No
Materials Analysis

Notes:
  1. Other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales.
  2. Didn't Find What You Need? Ask our applications engineers. Expert assistance in finding parts, usually within one business day.
  3. Part number suffixes: T or T&R = tape and reel; + = RoHS/lead-free; # = RoHS/lead-exempt; -D = drypack; -U/+U on DS parts = cut tape. More: See Full Data Sheet or Maxim Product Naming Conventions.
  4. * Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.

More Information

New Product Press Release 2002-11-21 ]


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Key Features
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Key Specifications
Diagram
Notes and Comments
  Data Sheet
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Rev 4; 2006-01-27
This page last modified: 2009-10-13


 


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