Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe

Active: In Production.

The MAX9173 quad low-voltage differential signaling (LVDS) line receiver is ideal for applications requiring high data rates, low power, and low noise. The MAX9173 is guaranteed to receive data at speeds up to 500Mbps (250MHz) over controlled-impedance media of approximately 100Ω. The transmission media can be printed circuit (PC) board traces or cables.

The MAX9173 accepts four LVDS differential inputs and translates them to LVCMOS/LVTTL outputs. The MAX9173 inputs are high impedance and require an external termination resistor when used in a point-to-point connection.

The device supports a wide common-mode input range of 0.05V to V_CC - 0.05V, allowing for ground potential differences and common-mode noise between the driver and the receiver. A fail-safe feature sets the output high when the inputs are open, or when the inputs are undriven and shorted or undriven and parallel terminated. The EN and EN-bar inputs control the high-impedance outputs. The enables are common to all four receivers. Inputs conform to the ANSI TIA/EIA-644 LVDS standard. The flow-through pinout simplifies board layout and reduces crosstalk by separating the LVDS inputs and LVCMOS/LVTTL outputs. The MAX9173 operates from a single 3.3V supply, and is specified for operation from -40°C to +85°C. Refer to the MAX9121/MAX9122 data sheet for lower jitter quad LVDS receivers with parallel fail-safe. Refer to the MAX9123 data sheet for a quad LVDS line driver with flow-through pinout.

The device is available in 16-pin TSSOP, SO, and space-saving thin QFN packages.

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