10-Bit Bus LVDS Deserializers

Active: In Production.

The MAX9206/MAX9208 deserializers transform a highspeed serial bus low-voltage differential signaling (BLVDS) data stream into 10-bit-wide parallel LVCMOS/LVTTL data and clock. The deserializers pair with serializers such as the MAX9205/MAX9207, which generate a serial BLVDS signal from 10-bit-wide parallel data. The serializer/deserializer combination reduces interconnect, simplifies PCB layout, and reduces board size.

The MAX9206/MAX9208 receive serial data at 450Mbps and 600Mbps, respectively, over board traces or twisted-pair cables. These devices combine frequency lock, bit lock, and frame lock to produce a parallel-rate clock and word-aligned 10-bit data. Serialization eliminates parallel bus clock-to-data and data-to-data skew.

A power-down mode reduces typical supply current to less than 600µA. Upon power-up (applying power or driving active-low PWRDN high), the MAX9206/MAX9208 establish lock after receiving synchronization signals or serial data from the MAX9205/MAX9207. An output enable allows the outputs to be disabled, putting the parallel data outputs and recovered output clock into a highimpedance state without losing lock.

The MAX9206/MAX9208 operate from a single +3.3V supply and are specified for operation from -40°C to +85°C. The MAX9206/MAX9208 are available in 28-pin SSOP packages.

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