DS21Q44

Enhanced Quad E1 Framer

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Description

The DS21Q44 E1 is an enhanced version of the DS21Q43 quad E1 framer. The DS21Q44 contains four framers that are configured and read through a common microprocessor-compatible parallel port. Each framer consists of a receive framer, receive elastic store, transmit formatter, and transmit elastic store. All four framers in the DS21Q44 are totally independent; they do not share a common framing synchronizer. The transmit and receive sides of each framer are also totally independent. The dual two-frame elastic stores contained in each of the four framers can be independently enabled and disabled as required. The device fully meets all of the latest E1 specifications including CCITT/ITU G.704, G.706, G.962, and I.431 as well as ETS 300 011 and ETS 300 233.
 

Data Sheet

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Key Features

  • Four E1 (CEPT or PCM-30)/ISDN-PRI framing transceivers
  • All four framers are fully independent; transmit and receive sections of each framer are fully independent
  • Frames to FAS, CAS, CCS, and CRC4 formats
  • Each of the four framers contain dual twoframe elastic-store slip buffers that can connect to asynchronous backplanes up to 8.192MHz
  • 8-bit parallel control port that can be used directly on either multiplexed or nonmultiplexed buses (Intel or Motorola)
  • Easy access to Si and Sa bits
  • Extracts and inserts CAS signaling
  • Large counters for bipolar and code violations, CRC4 code word errors, FAS word errors, and E-bits
  • Programmable output clocks for Fractional E1, per channel loopback, H0 and H12 applications
  • Integral HDLC controller with 64-byte buffers configurable for Sa bits or DS0 operation
  • Detects and generates AIS, remote alarm, and remote multiframe alarms
  • Pin compatible with DS21Q42 enhanced quad T1 framer
  • 3.3V supply with 5V tolerant I/O; low-power CMOS
  • Available in 128-pin TQFP package
  • IEEE 1149.1 support
   
   

Diagram

DS21Q44: Functional Diagram
Functional Diagram

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Rev 1; 2002-06-26
This page last modified: 2009-10-21




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