3.3V Bit Error Rate Tester (BERT)

Active: In Production.

The DS21372 Bit Error Rate Tester (BERT) is a software-programmable test pattern generator, receiver, and analyzer capable of meeting the most stringent error performance requirements of digital transmission facilities. Two categories of test pattern generation (pseudorandom and repetitive) conform to CCITT/ITU O.151, O.152, O.153, and O.161 standards. The DS21372 operates at clock rates ranging from DC to 20MHz. This wide range of operating frequency allows the DS21372 to be used in existing and future test equipment, transmission facilities, switching equipment, multiplexers, DACs, routers, bridges, CSUs, DSUs, and CPE equipment.

The DS21372 user-programmable pattern registers provide the unique ability to generate loopback patterns required for T1, Fractional-T1, Smart Jack, and other test procedures. Hence the DS21372 can initiate the loopback, run the test, check for errors, and, finally, deactivate the loopback.

The DS21372 consists of four functional blocks: the pattern generator, pattern detector, error counter, and control interface. The DS21372 can be programmed to generate any pseudorandom pattern with length up to 2³²-1 bits (see table 5, note 9 in data sheet) or any user-programmable bit pattern from 1 to 32 bits in length. Logic inputs can be used to configure the DS21372 for applications requiring gap clocking such as Fractional-T1, Switched-56, DDS, normal framing requirements, and per-channel test procedures. In addition, the DS21372 can insert single or 10^-1 to 10^-7 bit errors to verify equipment operation and connectivity.

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