Quad LVDS Line Receivers with Integrated Termination

Active: In Production.

The MAX9125/MAX9126 quad low-voltage differential signaling (LVDS) line receivers are ideal for applications requiring high data rates, low power, and reduced noise. The MAX9125/MAX9126 are guaranteed to receive data at speeds up to 500Mbps (250MHz) over controlled-impedance media of approximately 100Ω. The transmission media may be printed circuit (PC) board traces or cables.

The MAX9125/MAX9126 accept four LVDS differential inputs and translate them to 3.3V CMOS outputs. The MAX9126 features integrated parallel termination resistors (nominally 115Ω), which eliminate the requirement for four discrete termination resistors and reduce stub length. The MAX9125 inputs are high impedance and require an external termination resistor when used in a point-to-point connection.

The devices support a wide common-mode input range of 0.05V to 2.35V, allowing for ground potential differences and common-mode noise between the driver and the receiver. A fail-safe feature sets the output high when the inputs are open, or when the inputs are undriven and shorted or parallel terminated. The EN and EN-bar inputs control the high-impedance output and are common to all four receivers. Inputs conform to the ANSI TIA/EIA-644 LVDS standard. The MAX9125/ MAX9126 operate from a single +3.3V supply, are specified for operation from -40°C to +85°C, and are available in 16-pin TSSOP and SO packages. Refer to the MAX9124 data sheet for a quad LVDS line driver.

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