MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier

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Status Explanations for product status codes

Part Number Status
MAX105 Active: In Production. But some versions of the family are subject to Last Time Buy. See Ordering Information.

Description

The MAX105 is a dual, 6-bit, analog-to-digital converter (ADC) designed to allow fast and precise digitizing of in-phase (I) and quadrature (Q) baseband signals. The MAX105 converts the analog signals of both I and Q components to digital outputs at 800Msps while achieving a signal-to-noise ratio (SNR) of typically 37dB with an input frequency of 200MHz, and an integral nonlinearity (INL) and differential nonlinearity (DNL) of ±0.25 LSB. The MAX105 analog input preamplifiers feature a 400MHz, -0.5dB, and a 1.5GHz, -3dB analog input bandwidth. Matching channel-to-channel performance is typically 0.04dB gain, 0.1 LSB offset, and 0.2 degrees phase. Dynamic performance is 36.4dB signal-to-noise plus distortion (SINAD) with a 200MHz analog input signal and a sampling speed of 800MHz. A fully differential comparator design and encoding circuits reduce out-of-sequence errors, and ensure excellent metastable performance of only one error per 1016 clock cycles.

In addition, the MAX105 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two's complement format. The MAX105 operates from a +5V analog supply and the LVDS output ports operate at +3.3V. The data converter's typical power dissipation is 2.6W. The device is packaged in an 80-pin, TQFP package with exposed paddle, and is specified for the extended (-40° C to +85°C) temperature range. For a lower-speed, 400Msps version of the MAX105, please refer to the MAX107 data sheet.
 

Data Sheet

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An evaluation kit is available: MAX105EVKIT

Key Features

  • Two Matched 6-Bit, 800Msps ADCs
  • Excellent Dynamic Performance
    • 36.4dB SINAD at fIN ≈ 200MHz and
    • fCLK ≈ 800MHz
  • Typical INL and DNL: ±0.25 LSB
  • Channel-to-Channel Phase Matching: ±0.2°
  • Channel-to-Channel Gain Matching: ±0.04dB
  • 6:12 Demultiplexer reduces the Data Rates to 400MHz
  • Low Error Rate: 1016 Metastable States at 800Msps
  • LVDS Digital Outputs in Two's Complement Format
 

Applications/Uses

  • Communication Systems
  • Test Instrumentation
  • VSAT Receivers
  • Wireless Local Area Networks (WLANs)
   

Key Specifications:

High-Speed ADCs (> 5Msps)
Part Number Input Chan. Resolution
(bits)
Sample Rate
(Msps)
AC Specs
(MHz)
SFDR
(dBc)
ENOB
(bits)
SINAD
(dB)
SNR
(dB)
THD
(dB)
INL
(±LSB)
DNL
(±LSB)
Full Pwr. BW
(MHz)
ICC
(mA)
Data Bus Interface Smallest Available Pckg.
(mm2)
Budgetary Price
max ≥ @ fIN min min min typ max w/pins See Notes
MAX105  2 6 800 200 45 5.8 36.4 37 -44.5 0.2 0.25 400 650
µP/8
Demuxed
LVPECL
196 $35.95 @1k
See All High-Speed ADCs (> 5Msps) (74)
Pricing Notes:
This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific prices and delivery, please see the price and availability page or contact an authorized distributor.


Diagram

MAX105: Pin Configuration
Pin Configuration

More Information

New Product Press Release 2001-05-29 ]

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Information Index

Document Ref.: 19-2006 Rev 0; 2001-05-30
This page last modified: 2009-11-09




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