MAX3140

SPI/MICROWIRE-Compatible UART with Integrated True Fail Safe RS-485/RS-422 Transceivers

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Active: In Production.

Description

The MAX3140 is a complete universal asynchronous receiver-transmitter (UART) and a true fail-safe RS-485/RS-422 transceiver combined in a single 28-pin QSOP package for space-, cost-, and power-constrained applications. The MAX3140 saves additional board space as well as microcontroller (µC) I/O pins by featuring an SPI™/QSPI™/MICROWIRE™-compatible serial interface. It is pin-programmable for configuration in all RS-485/RS-422 networks.

The MAX3140 includes a single RS-485/RS-422 driver and receiver featuring true fail-safe circuitry, which guarantees a logic-high receiver output when the receiver inputs are open or shorted. This feature provides immunity to faults without requiring complex termination. The MAX3140 provides software-selectable control of half- or full-duplex operation, data rate, slew rate, and transmitter and receiver phase. The RS-485 driver slew rate is programmable to minimize EMI and results in maximum data rates of 115kbps, 500kbps, and 10Mbps. Independent transmitter/receiver phase control enables software correction of twisted-pair polarity reversal. A 1/8-unit-load receiver input impedance allows up to 256 transceivers on the bus.

The MAX3140's UART includes an oscillator circuit derived from an external crystal, and a baud-rate generator with software-programmable divider ratios for all common baud rates from 300 baud to 230k baud. The UART features an 8-word-deep receive FIFO that minimizes processor overhead and provides a flexible interrupt with four maskable sources, including address recognition on 9-bit networks. Two control lines are included for hardware handshaking-one input and one output.

The MAX3140 operates from a single +5V supply and typically consumes only 645µA with the receiver active. Hardware-invoked shutdown reduces supply current to only 20µA. The UART and RS-485/RS-422 functions can be used together or independently since the two functions share only supply and ground connections (the MAX3140 is hardware- and software-compatible with the MAX3100 and MAX3089).
 

Data Sheet

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Key Features

  • Integrated UART and RS-485/RS-422 Transceiver in a Single 28-Pin QSOP
  • SPI/MICROWIRE-Compatible Interface Saves µC I/O Pins
  • True Fail-Safe Receiver Output Eliminates Complex Network Termination
  • Pin-Programmable RS-485/RS-422 Features
    • Half/Full-Duplex Operation
    • Slew-Rate Limiting for Reduced EMI
    • 115kbps/500kbps/10Mbps Data Rates
    • Receiver/Transmitter Phase for Twisted-Pair Polarity Reversal
  • Full-Featured UART
    • Programmable Up to 230k baud with a 3.6864MHz Crystal
    • 8-Word Receive FIFO Minimizes Processor Overhead
    • 9-Bit Address-Recognition Interrupt
  • Allows Up to 256 Transceivers on the Bus
  • Low 20µA Hardware Shutdown Mode
  • Hardware/Software-Compatible with MAX3100 and MAX3089
 

Applications/Uses

  • Embedded Systems
  • HVAC and Building Control
  • Industrial Control Local Area Networks
  • Intelligent Instruments
  • Point-of-Sale (POS) Devices
  • Transceivers for EMI-Sensitive Applications
   

Key Specifications:

SPI/Microwire-Compatible UARTs
Part Number µP I/F Channels ICC
(mA)
VSUPPLY
(V)
Package/Pins Smallest Available Pckg.
(mm2)
Oper. Temp.
(°C)
Budgetary Price
typ max w/pins See Notes
MAX3140  SPI and Microwire Compatible 1 0.7 5
QSOP/28
61.9
-40 to +85
0 to +70
$4.42 @1k
See All SPI/Microwire-Compatible UARTs (8)
Pricing Notes:
This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific prices and delivery, please see the price and availability page or contact an authorized distributor.


Diagram

MAX3140: Typical Application Circuit
Typical Application Circuit

Notes and Comments

True Fail-Safe Receiver Output, Programmable Up to 230k baud with a 3.6864MHz Crystal, 8-Word Receive FIFO Minimizes Processor Overhead, 9-Bit Address-Recognition Interrupt

More Information

New Product Press Release 1999-05-11 ]

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Information Index

Document Ref.: 19-1453 Rev 1; 2010-10-19
This page last modified: 2010-10-19




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