Tech Brief 35: Building a Clock Fail Detector Using a Delay Line
Abstract: In certain electronic equipment, measures must be taken to ensure that the equipment operates correctly even when there is a failure in a subsystem of the equipment. A good example is a Telecom router. If a clock driving the router fails, circuitry is required to detect this and route in an alternate clock signal if possible. This application brief describes how to design a clock fail circuit using a DS1000 delay line (now replaced with the DS1100). Two alternative examples are given. One uses a delay line and digital logic to generate a digital fail signal indicating the presence or loss of a clock signal. A second application is described where this circuit, in combination with some simple switching logic, can not only detect the functionality of a systems clock, but automatically switch in an alternate clock if the primary clock fails.
The application note you have requested is available in Acrobat PDF format:
Automatic Updates
Would you like to be automatically notified when new application notes are published in your areas of interest? Sign up for EE-Mail™.
Download, PDF Format