Abstract: Complex digital systems may need multiple system clocks with precise phase-relationships to meet system-timing clocks. This application notes describes a method to generate phased clocks using delay lines. The application note you have requested is available in Acrobat PDF format: APPLICATION NOTE 880: Tech Brief 31: Using Delay Lines to Generate Multi-Phased Clocks (PDF, 112kB) A free Acrobat PDF reader is available from: http://www.adobe.com/products/acrobat/readstep.html Related Parts   APP 880: Dec 12, 2001 DS1004 5-Tap High-Speed Silicon Delay Line Full Data Sheet (PDF, 55kB) DS1005 5-Tap Silicon Delay Line Full Data Sheet (PDF, 63kB) DS1007 7-in-1 Silicon Delay Line Full Data Sheet (PDF, 57kB) DS1023 8-Bit Programmable Timing Element Full Data Sheet (PDF, 256kB) Free Samples DS1110 10-Tap Silicon Delay Line Full Data Sheet (PDF, 120kB) Free Samples Automatic Updates Would you like to be automatically notified when new application notes are published in your areas of interest? Sign up for EE-Mail™. We Want Your Feedback!   Download, PDF Format (112kB)  AN880, AN 880, APP880, Appnote880, Appnote 880