Abstract: Interfacing 10Gbps current-mode logic (CML) signals using controlled-impedance microstrip signal paths on printed circuit cards requires appropriate material selection and careful attention to layout geometry in order to control crosstalk, jitter and signal integrity. The following example from the MAX3950 10Gbps 1:16 deserializer evaluation kit (EV kit) board illustrates some key points. The application note you have requested is available in Acrobat PDF format: APPLICATION NOTE 466: MAX3950: Printed Circuit Card Layout Considerations for 10Gbps Current Mode Logic Inputs on the MAX3950 EVKIT (PDF, 52kB) A free Acrobat PDF reader is available from: http://www.adobe.com/products/acrobat/readstep.html Related Parts   APP 466: Nov 14, 2001 MAX3950 +3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs Full Data Sheet (PDF, 392kB) Automatic Updates Would you like to be automatically notified when new application notes are published in your areas of interest? Sign up for EE-Mail™. We Want Your Feedback!   Download, PDF Format (52kB)  AN466, AN 466, APP466, Appnote466, Appnote 466