Abstract: This application note discusses the effects of power-supply noise interference on PLL-based clock generators. It describes several measurement techniques for evaluating the resulting DJ (deterministic jitter). Relationships are derived outlining how frequency-domain spur measurements can be used to evaluate timing jitter behavior. Laboratory bench-test results are used to compare the approaches, and demonstrate how to reliably assess the PSNR (power-supply noise rejection) performance of a reference clock generator.

The application note you have requested is available in Acrobat PDF format:

APPLICATION NOTE 4461: HFAN-04.5.5 Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers (PDF, 599kB)

A free Acrobat PDF reader is available from:
http://www.adobe.com/products/acrobat/readstep.html

Related Parts APP 4461: May 11, 2009

MAX3624 Low-Jitter, Precision Clock Generator with Four Outputs Full Data Sheet
(PDF, 428kB)

MAX3625 Low-Jitter, Precision Clock Generator with Three Outputs Full Data Sheet
(PDF, 368kB)

MAX3627 +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs Full Data Sheet
(PDF, 620kB)

MAX3629 +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs Full Data Sheet
(PDF, 540kB)

MAX3679 +3.3V, Low-Jitter Crystal to LVPECL Clock Generator Full Data Sheet
(PDF, 396kB)

Automatic Updates
Would you like to be automatically notified when new application notes are published in your areas of interest? Sign up for EE-Mail™.

Download, PDF Format (599kB)
AN4461, AN 4461, APP4461, Appnote4461, Appnote 4461