Abstract: Application Note 306 provides the design requirements for implementing a three channel drop and insert application using the Dallas Semiconductor/Maxim DS2141A T1 framer or DS2143 E1 framer.
Notes:
A "looped-timed" application is shown.
This application assumes the dropped channels occupy the same timeslots as the inserted channels.
The idle registers in the DS1241A/43/51/53 can be used to fill unused (if any) channels.
The used channels do not need to be contiguous nor do they need to be only one channel wide.
The line interface function is included onboard the DS2151 and DS2153 devices.
The delay is used to adjust the clock to account for the delay in generation of the signals that create the bursty clock.
Additional channels can be added by allowing the RCHCLK signal to be driven into a counter and decoded; the decoded signal would then be used to provide additional selects for the decoder and mux.
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