Abstract: The MAX3670 low-jitter clock generator is a monolithic phase-locked loop (PLL) that uses an external high-Q voltage-controlled oscillator (VCO) to create a very low jitter clock signal phase-locked to a system clock input. It is ideal for SONET OC-48 or OC-192 applications requiring a very low jitter 156 MHZ or 622MHz clock signal. When used with a low-jitter voltage-controlled SAW oscillator (VCSO) or a voltage-controlled crystal oscillator (VCX), the total system jitter can be less than 1 psrms. This design note provides analysis and examples that address optimal PLL configuration, including external component values, internal divider settings, and internal phase detector gain for low-jitter applications. The application note you have requested is available in Acrobat PDF format: APPLICATION NOTE 1032: MAX3670: Loop-Filter Configuration for the MAX3670 Low-Jitter PLL Reference Clock Generator (PDF, 57kB) A free Acrobat PDF reader is available from: http://www.adobe.com/products/acrobat/readstep.html Related Parts   APP 1032: Jun 08, 2001 MAX3670 Low-Jitter 155MHz/622MHz Clock Generator Full Data Sheet (PDF, 204kB) Free Samples Automatic Updates Would you like to be automatically notified when new application notes are published in your areas of interest? Sign up for EE-Mail™. We Want Your Feedback!   Download, PDF Format (57kB)  AN1032, AN 1032, APP1032, Appnote1032, Appnote 1032