Keywords: Power supply noise interference, PLL based clock generators, deterministic jitter, power-supply noise rejection Related Parts
APPLICATION NOTE 4461
HFAN-04.5.5 Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers
By:
Sharon Wang
May 11, 2009
Abstract: This application note discusses the effects of power-supply noise interference on PLL-based clock generators. It describes several measurement techniques for evaluating the resulting DJ (deterministic jitter). Relationships are derived outlining how frequency-domain spur measurements can be used to evaluate timing jitter behavior. Laboratory bench-test results are used to compare the approaches, and demonstrate how to reliably assess the PSNR (power-supply noise rejection) performance of a reference clock generator.
The document you have requested is available in Acrobat PDF format:
APPLICATION NOTE 4461: HFAN-04.5.5 Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers