Keywords: clock and data recovery, cdr, multiple data rates, jitter peaking, acquisition time, regenerator and receiver, multi-rate cdr, applications, phase lock loop, PLL, filter capacitor, data recovery, limiting amplifier, IC Related Parts
APPLICATION NOTE 1993
MAX3872: Choosing an Optimal Filter Capacitor for the MAX3872 Multi-Rate CDR
Apr 24, 2003
Abstract: The MAX3872 is a clock and data recovery (CDR) with limiting amplifier IC, designed to operate at multiple data rates. It is intended for regenerator and receiver applications and contains a fully integrated phase-locked loop (PLL). The PLL is a second-order feedback system that requires an external capacitor for the loop filter. This capacitor is a significant factor in multi-rate designs because it determines the acquisition time and jitter peaking at a particular data rate. This design note is intended as a guide for choosing the optimal filter capacitor to minimize acquisition time, while meeting the jitter peaking specifications at all the data rates required for the application.
The document you have requested is available in Acrobat PDF format:
APPLICATION NOTE 1993: MAX3872: Choosing an Optimal Filter Capacitor for the MAX3872 Multi-Rate CDR