| Amplifier and Comparator Circuits |
| Telecom |
| DS34T101 DS34T102 DS34T104 DS34T108 | FDL Network Loopback Support Using TDMoP Devices |
| Communications Circuits |
| MAX3272 MAX3624 | Assess Power-Supply Noise Rejection in Low-Jitter PLL Clock Generators |
| DS33X162 DS33X82 DS33X42 DS33X161 DS33X81 DS33X41 DS33W11 DS33W41 DS33R11 DS33Z11 | Carrier Ethernet Service Demarcation in Optical Networks |
| DS34T101 DS34T104 DS34T108 DS34S101 DS34S102 DS34S104 DS34S108 DS34T102 | Interoperability of Maxim's TDM-over-Packet (TDMoP) Devices with Other Vendors' TDMoP Devices |
| DS33W11 DS33W41 DS33X11 DS33X41 DS33X42 DS33X81 DS33X82 DS33X161 DS33X162 | DS33X162 Product Family FAQ |
| DS34S101 DS34S102 DS34S104 DS34S108 DS34T101 DS34T102 DS34T104 DS34T108 | How to Use Jitter Buffers on TDMoP Products to Compensate for Packet-Delay Variation (PDV) |
| DS33M30 DS33M31 DS33M33 | Using Ethernet over PDH in SONET/SDH Networks |
| MAX1968 MAX3667 DS3152 MAX1932 DS3150 DS3153 MAX3645 MAX3657 DS3154 DS3151 | HFTA-09.0: T3/E3/STS-1 Fiber Optic Extension |
| DS2152 DS2154 DS26528 DS26524 DS26522 DS26521 DS26519 DS26518 | Tech Brief 7: DS2152 and DS2154 8MHz System Clock Operation |
| DS21Q48 DS21Q348 DS2156 DS21352 DS2148 DS21Q55 DS2152 DS21554 DS2155 DS21552 DS21348 DS2148 DS2154 DS21354 | Power-Fault Protection Layout |
| DS21Q554 DS21Q354 DS2154 DS21354 DS21554 | DS21354/DS21554 vs. DS2154 Single Chip Transceivers |
| DS2152 DS21552 DS21352 | DS21352/DS21552 versus DS2152 Single Chip Transceiver |
| DS21Q42 DS21Q41B | DS21Q42 vs. DS21Q41B |
| DS2152 DS2154 | DS2152, DS2154 Clock Map |
| DS2153 DS2151 | Converting the DS2151/DS2153 Demo Kits |
| DS2152 DS2154 DS2154 DS2152 | Converting the DS2152/DS2154 Demo Kits |
| DS2151 DS2141A | DS2141A, DS2151 Alarm Set and Clear Criteria |
| DS2141A | DS2141A Creating a DS/ESF Channel Service Unit |
| DS2153 DS2143 DS2151 DS2141A | DS2141A, DS2143, DS2151, DS2153 Interfacing to a Nonmultiplexed Bus |
| DS2154 DS2152 | DS2152, DS2154 Interfacing to the IGT ALL1 SAR (WAC-021-C) |
| DS2151 DS2153 | DS2151, DS2153 Interfacing to the PMC-Sierra PM7345 |
| DS2151 DS2143 DS2141A DS2153 | DS2141A, DS2143, DS2151, DS2153 Interfacing to the Siemens PEB2045 |
| DS2153 DS2141A DS2143 DS2151 | DS2141A, DS2143, DS2151, DS2153 Interfacing to the Mitel MT8980D |
| DS2141A DS2153 DS2143 DS2151 | DS2141A, DS2143, DS2151 and DS2153 Interfacing to the SGS-Thomson M3488 |
| DS2153 DS2151 DS2141A DS2143 | DS2141A, DS2143 Three Channel Drop and Insert |
| DS2153 DS2151 | DS2151, DS2153 Interfacing to the ADSP-2181 |
| DS2151 DS2153 DS2141 DS21Q41 DS21Q43 | DS2141, DS21Q41, DS21Q43 8-MHz System Clock Operation |
| DS26518 DS26519 DS26521 DS26522 DS2141 DS2143 DS21Q41 DS2153 DS26528 DS2152 DS2154 DS21Q43 DS2151 DS26524 | Legacy T1/E1 8MHz Backplane Operation |
| General Engineering Topics |
| DS33X162 DS33X82 DS33X42 DS33X161 DS33X81 DS33X41 DS33W11 DS33W41 DS33R11 DS33Z11 | Carrier Ethernet Service Demarcation in Optical Networks |
| Measurement Circuits |
| MAX3272 MAX3624 | Assess Power-Supply Noise Rejection in Low-Jitter PLL Clock Generators |
| Optoelectronics |
| General: Optical Systems |
| MAX1968 MAX3667 DS3152 MAX1932 DS3150 DS3153 MAX3645 MAX3657 DS3154 DS3151 | HFTA-09.0: T3/E3/STS-1 Fiber Optic Extension |
| Oscillators/Delay Lines/Timers/Counters |
| DS3174 DS3164 DS3252 DS3163 DS3162 DS3168 DS3251 DS3182 DS3172 DS3166 DS3183 DS3253 DS3254 DS3171 DS3173 DS3181 DS3184 DS3161 | Clock-Rate-Adapter (CLAD) Features for DS325X, DS316X, DS317X, and DS318X |
| Power-Supply Circuits |
| APP NOTES FOR: Network/Telecom/WLAN |
| MAX3272 MAX3624 | Assess Power-Supply Noise Rejection in Low-Jitter PLL Clock Generators |
| Signal Generation Circuits |
| MAX3272 MAX3624 | Assess Power-Supply Noise Rejection in Low-Jitter PLL Clock Generators |
| Switches and Multiplexers |
| DS33W11 DS33W41 DS33X11 DS33X41 DS33X42 DS33X81 DS33X82 DS33X161 DS33X162 | DS33X162 Product Family FAQ |
| T/E Carrier and Packetized |
| Carrier Ethernet |
| DS33X162 DS33X82 DS33X42 DS33X161 DS33X81 DS33X41 DS33W11 DS33W41 DS33R11 DS33Z11 | Carrier Ethernet Service Demarcation in Optical Networks |
| DS33R11 | DS33R11 Multichip-Module BSDL Testing |
| DS33M30 DS33M31 DS33M33 | Using Ethernet over PDH in SONET/SDH Networks |
| DS33R41 | DS33R41 Multichip-Module BSDL Testing |
| DS33Z11 DS33Z41 DS33R41 DS33Z44 DS33R11 | Ethernet-over-PDH Technology Overview |
| DS33Z44 DS33Z11 | EEPROM Programming Instructions for DS33Z11/DS33Z44 |
| DS33Z41 DS33Z44 DS33Z11 | DS33Z11 - Ethernet LAN To Unframed T1/E1 WAN Bridge |
| Other |
| DS31256 | Enabling Fractional-T1(FT1) Loopback Detection on the DS31256 |
| DS31256 | DS31256 PCI Bus Utilization |
| DS3150 DS21Q55 DS3112 DS31256 DS21FF4 DS26528 DS21FT42 DS21FF42 | Examples of DS31256 Applications |
| DS31256 | DS31256 -- Example Code for Registers Dump |
| DS31256 | Internal Test Registers for the DS31256
|
| DS31256 | DS31256 HDLC Controller Step-by-Step Configuration—Bridge Mode |
| DS31256 | DS31256 HDLC Controller Step-by-Step Configuration—Configuration Mode |
| DS31256 | DS31256 Loopback Modes |
| DS31256 | DS31256 Gapped Clock Applications |
| DS2172 | Interfacing User Devices and the DST1E1DK SCT Design Kit |
| DS21372 DS2172 | DS2172 BERT Interface to all Dallas Framers and Transceivers |
| DS2172 | DS2172 Pattern Synchronization |
| DS2172 | DS2172 Simplified Receiver Operation |
| T/E Carrier |
| DS26518 | Transmit Pulse Control on the DS26518 T1/E1/J1 Transceiver |
| DS26528 DS26524 DS26522 DS26521 | How to Use the Bit-Error-Rate Tester (BERT) on the DS2652x STCs |
| DS26303 | Initilization and Configuration of the DS26303 LIU |
| DS26303 IDT82V2048 | DS26303 Short-Haul Line Interface Unit vs. IDT82V2048 |
| LXT384 DS26303 | DS26303 Short-Haul Line Interface Unit vs. LXT384 |
| DS26522 DS26521 | DS26522 JTAG Scan Chain Mapping |
| DS26528 DS26524 | Initialization and Configuration of the DS26528 Transceiver |
| DS3252 DS3251 DS3254 DS3253 | Using Software to Shape the Transmit Pulse of the DS325x LIUs |
| DS3172 DS3171 DS3183 DS3173 DS3181 DS3182 DS3184 DS3174 | Measuring and Improving Return Loss on the DS317x and DS318x T3/E3/STS-1 LIUs |
| DS21554 DS21Q44 DS21552 DS21602 DS21Q42 DS21Q352 DS21FF42 DS21352 DS21FT42 DS21354 DS21FF44 DS21Q354 DS21Q554 DS21FT44 DS3112 DS21Q552 DS3120 DS31256 | Interleaved Bus Operation |
| DS26524 DS26528 | DS26528 and DS26524 Transmit Pulse Control |
| DS3112 | DS3112 LRCLKx Low Speed Clock Recovery Operation
|
| DS21458 DS21Q55 DS2155 DS26521 DS26528 DS21455 | DS2155 and DS26521 Software Comparison |
| DS3150 DS3174 DS3182 DS3171 DS3154 DS3184 DS3172 DS3251 DS3252 DS3253 DS3152 DS3254 DS3181 DS3170 DS3183 DS3151 DS3153 DS3173 | Measuring Return Loss Using the Advantest R3132 Spectrum Analyzer |
| DS26324 DS26334 | DS26334 and DS26324 Transmit Pulse Control |
| DS21Q55 DS26528 DS21458 DS21455 DS2155 | DS21458 Quad and DS26528 Octal Transceiver Software Comparison |
| DS3174 DS3164 DS3252 DS3163 DS3162 DS3168 DS3251 DS3182 DS3172 DS3166 DS3183 DS3253 DS3254 DS3171 DS3173 DS3181 DS3184 DS3161 | Clock-Rate-Adapter (CLAD) Features for DS325X, DS316X, DS317X, and DS318X |
| DS21455 DS2155 | JJ-20.11-Compatible Interface for the DS2155 and DS21455 SCTs |
| DS3253 DS3150 DS21448 DS3254 DS3251 DS3252 DS21348 DS2148 DS3151 DS3152 DS3154 DS3153 | Configuring Dallas Semiconductor LIUs Without a Microcontroller
|
| DS3153 DS3172 DS3151 DS21552 DS3181 DS21354 DS3150 DS3171 DS3254 DS3183 DS3182 DS2155 DS3252 DS21352 DS3251 DS21554 DS3173 DS3174 DS3154 DS3184 DS3152 DS3253 DS3170 | Measuring Return Loss on T3/E3/STS-1 LIUs |
| DS2154 | DS2154 – Migrating from Revision A2 to D1 |
| DS26502 | DS26502 Hardware Mode |
| DS3252 DS3184 DS3253 DS3183 DS3181 DS3171 DS3254 DS3154 DS3174 DS3153 DS3152 DS3172 DS3151 DS3251 DS3182 DS3170 DS3150 DS3173 | Guidelines for Laying Out T3 and E3 Network Interfaces |
| DS3184 DS3181 DS3183 DS3182 | Configuration of CLAD for DS318x |
| DS2155 DS26502 | DS2155 and DS26502 Software Comparison |
| DS2155 DS21458 DS21458 DS2155 | DS2155 To DS21458 Migration |
| DS3150 | T3/E3/STS-1 Low Cost Repeater |
| DS2155 DS21354 DS2150 DS21Q55 DS21455 DS21Q554 DS21Q552 DS21458 DS21352 DS2159 DS21Q354 DS2158 DS21Q352 DS2156 DS21554 DS21552 | T1/E1 Loopback Operation for Dallas Semiconductor T1/E1/J1 transceivers |
| DS31256 DS3112 DS21FF44 DS3150 | DS31256 -- T3/E3 MUX/DS3112 Hardware Connections |
| DS3153 DS3152 DS3151 DS3150 DS3154 | Connecting the Agere Supermapper™ Device Family to Dallas T3 LIUs |
| DS2151 DS21Q554 DS2153 DS21552 DS2155 DS26401 DS21458 DS21Q352 DS21352 DS2154 DS21Q552 DS21Q55 DS26528 DS21Q354 DS2152 DS21354 DS21554 DS21455 | Elastic Store Operation |
| DS3153 DS3150 DS3152 DS3154 DS3151 | Connecting the Agere Ultramapper Device Family to Dallas T3/E3 LIUs |
| DS21Q354 DS21Q50 DS2155 DS21Q55 DS21552 DS21Q352 DS21554 DS21Q58 DS2196 DS21Q552 DS21Q554 DS2156 DS21352 DS21354 DS21Q59 | Selecting a T1/E1/J1 Single-Chip Transceiver |
| DS3144 DS3142 DS3153 DS3148 DS3151 DS3146 DS3152 DS31412 DS3143 DS3154 DS3141 | Interfacing the DS3144 Framer with the DS3154 LIU |
| MAX1968 MAX3667 DS3152 MAX1932 DS3150 DS3153 MAX3645 MAX3657 DS3154 DS3151 | HFTA-09.0: T3/E3/STS-1 Fiber Optic Extension |
| DS3152 DS3154 DS3153DK DS3151 DS3154DK DS3153 | Modifying the pulse shape of DS315x using Test Registers
|
| DS21Q55 DS21Q55 DS2156 DS2155 DS2156 DS2155 | DS2155, DS21Q55, DS2156 Programming SLC-96 |
| DK2000 DS2156 DS2156DK DK101 | Interfacing the DS2156 Utopia II Bus to Dallas Demo Kits |
| DS2156 DS2152 DS21458 DS21FT42 DS21352 DS21552 DS21Q42 DS2155 DS2151 DS21FF42 DS21Q55 | Switching Frame Mode In Live T1 Systems
|
| DS21412 DS2174 DS2146 DS2148 DS2143 DS2172 DS2142 DS2141 DS2144 | Bit Error Rate Testing the DS314x Series of DS3/E3 Framers
|
| DS3153 DS3152 DS3150 DS3151 DS3154 | Redundancy Protection for T3/E3/STS-1 Networks
|
| DS2155 | Network Interface and Circuit Designs for Secondary Protection of the DS2155 Single-Chip Transceiver |
| DS3154 DS21Q55 | Measuring Telecom Systems Against a Pulse Mask Template |
| DS21Q352 DS2148 DS2155 DS21Q354 DS21348 DS21Q552 DS21Q554 | Maxim® Telecommunications Frequently Asked Questions |
| DS2152 DS2154 DS26528 DS26524 DS26522 DS26521 DS26519 DS26518 | Tech Brief 7: DS2152 and DS2154 8MHz System Clock Operation |
| DS2155 DS2152 DS2151 DS21FF42 DS2141A DS21FT42 DS21552 DS21Q352 DS21Q55 DS2156 DS21Q42 DS21Q552 DS21352 | Programming and Controlling the FDL on DS2141A, DS2151 |
| DS21348 DS2148 | DS2148/DS21348 Hardware Mode |
| DS21Q552 DS21Q554 DS21Q55 DS21Q352 DS21Q354 | DS21Qx5y BSDL Scan Chain Mapping |
| DS21Q48 DS21Q348 DS2156 DS21352 DS2148 DS21Q55 DS2152 DS21554 DS2155 DS21552 DS21348 DS2148 DS2154 DS21354 | Power-Fault Protection Layout |
| DS3152 DS315X DS3254 DS3153 DS3154 DS3252 DS3151 DS3253 DS3251 DS3150DK DS3150 | Modifying the E3 Template Compliance of the DS3150, DS315x and DS325x |
| DS26401 DS21458 DS21455 DS2155 DS21Q55 | DS2155 and DS26401 Software Comparison |
| DS21448 DS2148 DS21Q48 DS21Q348 DS21348 | Additional Pulse Amplitude Settings for DS2148, DS21348, DS21Q48, DS21Q348 and DS21448 |
| DS2155 DS21Q55 | Extended System Information Bus (ESIB) Control Application |
| DS21455 DS2155 DS21E55 DS21458 DS21Q55 | DS2155 Monitor Mode Design |
| DS3152 DS3154 DS3150 DS3153 DS3151 | T3/E3/STS-1 LIU Secondary Surge Protection Design |
| DS2155 DS3154 DS3152 DS3153 DS3151 DS21Q55 | Pulse Template Measurement |
| DS21Q59 DS21Q55 DS21Q50 DS21Qx5y | Design Migration from DS21Q55 to DS21Q50 or DS21Q59 |
| DS21Q50 DS21Q59 | DS21Q59 vs. DS21Q50 Quad E1 Transceivers |
| DS21Q55 DS21FT42 DS21552 DS21FT44 DS21Q554 DS21FF42 DS21Q552 DS21Q42 DS21352 DS2155 DS21E55 DS21Q354 DS21Q44 DS21354 DS2156 DS21FF44 DS21Q352 DS21554 | HDLC Configuration of Framers and Transceivers |
| DS2153 DS21354 DS21Q354 DS2150 DS2155 DS21Q44 DS21FT44 DS2154 DS21554 DS21Q554 DS21Q50 DS21Q43 DS21FF44 DS2156 | E1 Operation of Dallas Semiconductor Framers and SCTs |
| DS21455 DS21458 DS2155 DS21Q50 DS21Q55 DS26528 DS31256 | DS31256 and T1/E1 Interface |
| DS2156 DS21Q55 DS2155 | DS2155 Internal BERT Programming |
| DS21554 DS2155 DS2148 DS21348 DS21352 DS21552 DS21354 | Hitless Protection Switching with 1+1 Redundancy |
| DS21348 DS2148 | Using DS2148/348 as Repeater |
| DS21348 DS2155 DS2156 DS21354 DS21Q348 | T1/E1/J1 Dual Connector Interface |
| DS2149 DS21Q552 DS21FT42 DS2148 DS21Q352 DS21Q42 DS2155 DS2152 DS21Q48 DS21552 DS21FF42 DS21Q55 DS21352 | J1 Japanese Standards |
| DS215354 DS21352 DS2155 DS2156 DS21554 DS215552 | Interfacing the DS2155 to the MPC8260 |
| DS21352 DS21602 DS21600 DS21554 DS21354 DS21610 DS21552 | Conversion Between T1 and E1
|
| DS3112 | DS3112 Clock Rates and Frequency Tolerances of the Transmit Clock |
| DS21Q50 | Simple, Low-Cost, 4-Port E1 Design Using DS21Q50
|
| DS21552 DS21Q352 DS21554 DS21Q55 DS21Q554 DS2155 DS21Q552 DS2352 DS21354 DS21Q354 | DS2155 vs. DS21x5y: Software and Hardware Considerations
|
| DS21552 DS2152 DS2149 DS2143 DS21354 DS2154 DS21349 DS21Q44 DS21352 DS2148 DS2141 DS2155 DS21554 DS21348 DS21Q41 | Using RCLK in a BITS/SSU Application |
| DS3150 | Replacing the TDK 78P7200/2241 with the DS3150 Line Interface Unit |
| DS21Q554 DS21Q354 DS2154 DS21354 DS21554 | DS21354/DS21554 vs. DS2154 Single Chip Transceivers |
| DS2152 DS21552 DS21352 | DS21352/DS21552 versus DS2152 Single Chip Transceiver |
| DS21X5Y | Interfacing the DS21x5y to the TMS320C54x |
| DS21Q42 DS21Q41B | DS21Q42 vs. DS21Q41B |
| DS21Q44 DS21Q43A | DS21Q44 vs. DS21Q43A |
| DS21552 DS21Q44 DS21554 DS21354 DS2154 DS21Q42 DS2152 DS21352 | DS21Q4x, DS215x, and DS21x5y Test Registers |
| DS2152 DS2154 | DS2152, DS2154 Clock Map |
| DS26521 DS26522 DS26524 DS26528 DS21352 DS21455 DS2151 DS3152 DS21Q59 DS3184 DS2154 DS21Q50 DS3154 DS3151 DS21349 DS3181 DS21Q348 DS2152 DS2156 DS21Q552 DS2153 DS21448 DS21Q58 DS21Q48 DS2148 DS3183 DS3150 DS2196 DS21354 DS2155 DS2149 DS21552 DS21348 DS21Q554 DS21458 DS3153 DS3182 DS21Q354 DS21554 DS21Q352 DS21Q55 | T1/E1 and T3/E3 Transformer Selection Guide |
| DS2154 DS2153 DS2154 DS2153Q | DS2154L vs. DS2153Q |
| DS2153 DS2151 | Converting the DS2151/DS2153 Demo Kits |
| DS2152 DS2154 DS2154 DS2152 | Converting the DS2152/DS2154 Demo Kits |
| DS21Q552 DS21Q352 DS2151 DS21FF42 DS21FT42 DS2152 DS21Q55 DS2141A DS2155 DS21552 DS21Q42 DS21352 | DS21352/552, DS2151, DS2152, DS2141A, DS21Q42 Programming SLC-96 |
| DS21Q44 DS21Q43 DS21Q42 DS21Q41 DS21FT44 DS21352 DS21FT42 DS21FF44 DS21554 DS2152 DS21354 DS21552 DS2151 DS2154 DS21FF42 DS2153 | T1/E1 Framer Initialization and Programming |
| DS2151 DS21x5y DS2154 DS2153 DS2155 DS2152 | DS2151, DS2153 Device Identification |
| DS2141A DS2151 | DS2141A, DS2151 D4 Framing Applications |
| DS2151 DS2141A | DS2141A, DS2151 Alarm Set and Clear Criteria |
| DS21352 DS2151 DS2155 DS21552 DS2152 | DS2151 Implementation of ANSI T1.231-1993 |
| DS21Q354 DS21Q44 DS21FT44 DS2152 DS21552 DS21Q352 DS21Q42 DS21554 DS2155 DS21FF42 DS21Q50 DS2150 DS21Q55 DS2151 DS2153 DS21FT42 DS2154 DS21Q55 DS21Q41 DS21FF44 DS21Q554 DS21352 DS21Q43 DS21354 | Transparent Operation on T1, E1 Framers and Transceivers |
| DS2153 | DS2153 Special Modes |
| DS2151 DS2175 DS2153 | DS2151 Special Modes |
| DS2141A | DS2141A Creating a DS/ESF Channel Service Unit |
| DS2153 DS2151 | DS2151, DS2153 Creating a T1/E1 Channel Service Unit |
| DS2153 DS2143 DS2151 DS2141A | DS2141A, DS2143, DS2151, DS2153 Interfacing to a Nonmultiplexed Bus |
| DS2151 DS2153 DS2155 DS21554 DS21552 DS2154 DS21352 DS21354 DS2152 | DS2151, DS2152, DS2153, DS2154 Dallas Single Chip Transceiver Crystal Selection Guide |
| DS2155 DS21352 DS21Q48 DS2148 DS2148 DS21Q348 DS2152 DS21348 DS21552 DS2154 DS21354 DS21554 DS2155 DS2156 | T1/E1 Network Interface Design |
| DS2151 DS2152 DS2153 DS2154 | DS2151, DS2152, DS2153, DS2154 T1/E1 Line Monitor |
| DS2154 DS2152 | DS2152, DS2154 Interfacing to the IGT ALL1 SAR (WAC-021-C) |
| DS2154 DS21354 DS21Q55 DS21552 DS2152 DS2155 DS21352 DS21554 | DS2152, DS2154, DS21x5Y, and DS2155 Interfacing to the MC68360 (QUICC32) |
| DS2151 DS2153 | DS2151, DS2153 Interfacing to the MC68MH360 QUICC32 |
| DS2152 DS2154 | DS2152, DS2154 Interfacing to the Siemens PXB4220 |
| DS2151 DS2153 | DS2151, DS2153 Interfacing to the PMC-Sierra PM7345 |
| DS2151 DS2143 DS2141A DS2153 | DS2141A, DS2143, DS2151, DS2153 Interfacing to the Siemens PEB2045 |
| DS2153 DS2141A DS2151 DS2142 | DS2141A, DS2142, DS2151, DS2153 Per-Channel Loopback |
| DS2153 DS2141A DS2143 DS2151 | DS2141A, DS2143, DS2151, DS2153 Interfacing to the Mitel MT8980D |
| DS2151 DS2153 | DS2151, DS2153 Interfacing to the PEB20320 |
| DS2151 DS2153 | DS2151, DS2153 Interfacing to the Hitachi HD64570 |
| DS21FT42 DS21Q352 DS21Q552 DS21552 DS21Q41 DS21Q42 DS2152 DS21FF42 DS2141A DS2151 DS21352 | D4 Framing and Signaling |
| DS21552 DS21Q41 DS21Q44 DS2141A DS21352 DS21Q42 DS2154 DS21554 DS21FT44 DS2151 DS21FT42 DS21354 DS21Q43 DS21Q554 DS21FF42 DS21Q352 DS2152 DS21Q354 DS21FF44 DS2143 DS2153 DS21Q552 DS21458 DS21455 DS26528 DS26524 DS26522 DS26521 DS26519 DS26518 | Interfacing to the Fractional T1 and E1 |
| DS2141A DS2153 DS2143 DS2151 | DS2141A, DS2143, DS2151 and DS2153 Interfacing to the SGS-Thomson M3488 |
| DS1000 DS21554 DS2153 DS21352 DS2155 DS2151 DS2152 DS21552 DS2154 DS21354 | DS2152, DS2154, DS2151, DS2153, DS21X5Y and DS2155 Three Channel Drop and Insert |
| DS2153 DS2151 DS2141A DS2143 | DS2141A, DS2143 Three Channel Drop and Insert |
| DS2153 DS2151 | DS2151, DS2153 Interfacing to the Brooktree Bt8221 and Bt8222 |
| DS2151 DS2153 | DS2151, DS2153 Interfacing to the AT&T T7270 |
| DS2153 DS2151 | DS2151, DS2153 Interfacing to the ADSP-2181 |
| DS2151 DS2153 DS2141 DS21Q41 DS21Q43 | DS2141, DS21Q41, DS21Q43 8-MHz System Clock Operation |
| DS26518 DS26519 DS26521 DS26522 DS2141 DS2143 DS21Q41 DS2153 DS26528 DS2152 DS2154 DS21Q43 DS2151 DS26524 | Legacy T1/E1 8MHz Backplane Operation |
| TDM over Packet |
| DS34T101 DS34T102 DS34T104 DS34T108 | FDL Network Loopback Support Using TDMoP Devices |
| DS34T101 DS34T104 DS34T108 DS34S101 DS34S102 DS34S104 DS34S108 DS34T102 | Interoperability of Maxim's TDM-over-Packet (TDMoP) Devices with Other Vendors' TDMoP Devices |
| DS34S101 DS34S102 DS34S104 DS34S108 DS34T101 DS34T102 DS34T104 DS34T108 | How to Use Jitter Buffers on TDMoP Products to Compensate for Packet-Delay Variation (PDV) |
| DS34T108 DS34T104 DS34T102 DS34T101 DS34S108 DS34S104 DS34S102 DS34S101 | How to Install NISTnet Software and Configure TDMoP Products to Run with It |
