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MAX3610
Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator


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Description
FULL DATA SHEET (PDF, 692kB)
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The MAX3610 is a low-jitter, high-performance, dual-rate clock generator optimized for 1Gbps/2Gbps/4Gbps Fibre-Channel applications. When connected with an external AT-cut crystal, the device generates a precision clock output by integrating a crystal oscillator with Maxim's low-noise phase-locked loop (PLL) providing a low-cost solution. By coupling Maxim's low-noise PLL design featuring a low-jitter generation VCO with an inexpensive fundamental mode crystal, the MAX3610 provides the optimum combination of low cost, flexibility, and high performance.

The MAX3610 output frequency is selectable. When using a 26.5625MHz crystal, the output clock rate can be set to either 106.25MHz or 212.5MHz. When operating at 106.25MHz, the typical phase jitter is 0.7psRMS from 12kHz to 20MHz. The MAX3610A has low-voltage positive-emitter-coupled logic (LVPECL) clock output drivers. The MAX3610B has low-voltage differential-signal (LVDS) clock output drivers. The MAX3610 output drivers can also be disabled.

The MAX3610 operates from a single +3.3V supply. The PECL version typically consumes 165mW, while the LVDS version typically consumes 174mW. Both devices are available in die form and have a 0°C to +85°C operating temperature range.

Key Features   Applications/Uses
  • Clock Output Frequencies: 106.25MHz or 212.5MHz
  • Phase Jitter: 0.7psRMS
  • LVPECL or LVDS Output
  • Excellent Power-Supply Noise Rejection
  • Supply Current:
    • 50mA at +3.3V Supply (LVPECL)
    • 53mA at +3.3V Supply (LVDS)
  • 0°C to +85°C Temperature Range
  • Optional Output Disable

 
  • Fibre Channel Hard Disk Drives
  • Fibre Channel Switches
  • Host Bus Adapters
  • Raid Controllers

    Key Specifications:   Clock Generators
    Part Number Nominal Input Reference (Crystal or CLK) (kHz) Input Reference Range (MHz) Output Frequencies (MHz) Output Type Number of Outputs Number of PLLs Programmability Output Jitter (ps) Supply Voltage (V) Package Operating Temp. Range (°C)
    MAX3610  26.5625 26.5625 106.25
    212.5
    LVDS
    LVPECL
    1 1 Divider Ratio 0.7 (RMS) 3.0 to 3.6 DICE SALES/0 0 to +85
    See All Clock Generators (22)

    Diagram
    MAX3610: Typical Operating Circuit
    Typical Operating Circuit

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    Document Ref.: 19-3286; Rev 0; 2004-05-14
    This page last modified: 2008-03-13




             


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