The MAX109, 2.2Gsps, 8-bit, analog-to-digital converter (ADC) enables the accurate digitizing of analog signals with frequencies up to 2.5GHz. Fabricated on an advanced SiGe process, the MAX109 integrates a high-performance track/hold (T/H) amplifier, a quantizer, and a 1:4 demultiplexer on a single monolithic die. The MAX109 also features adjustable offset, full-scale voltage (via REFIN), and sampling instance allowing multiple ADCs to be interleaved in time.
The innovative design of the internal T/H amplifier, which has a wide 2.8GHz full-power bandwidth, enables a flat-frequency response through the second Nyquist region. This results in excellent ENOB performance of 6.9 bits. A fully differential comparator design and decoding circuitry reduce out-of-sequence code errors (thermometer bubbles or sparkle codes) and provide excellent metastability performance (1014 clock cycles). This design guarantees no missing codes.
The analog input is designed for both differential and single-ended use with a 500mVP-P input-voltage range. The output data is in standard LVDS format, and is demultiplexed by an internal 1:4 demultiplexer. The LVDS outputs operate from a supply-voltage range of 3V to 3.6V for compatibility with single 3V-reference systems. Control inputs are provided for interleaving additional MAX109 devices to increase the effective system-sampling rate.
The MAX109 is offered in a 256-pin Super Ball-Grid Array (SBGA) package and is specified over the extended industrial temperature range (-40°C to +85°C).
Key Features
Applications/Uses
Ultra-High-Speed, 8-Bit, 2.2Gsps ADC
2.8GHz Full-Power Analog Input Bandwidth
Excellent Signal-to-Noise Performance
44.6dB SNR at fIN = 300MHz
44dB SNR at fIN = 1600MHz
Superior Dynamic Range at High-IF
61.7dBc SFDR at fIN = 300MHz
50.3dBc SFDR at fIN = 1600MHz
-60dBc IM3 at fIN1 = 1590MHz and fIN2 = 1610MHz
500mVP-P Differential Analog Inputs
6.8W Typical Power Including the Demultiplexer
Adjustable Range for Offset, Full-Scale, and Sampling Instance
50Ω Differential Analog Inputs
1:4 Demultiplexed LVDS Outputs
Interfaces Directly to Common FPGAs with DDR and QDR Modes
Download
E-Mail