The DS28CN01 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the Federal Information Publications (FIPS) 180-1/180-2 and ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The memory is organized as four pages of 32 bytes each. Data copy-protection and EPROM emulation features are supported for each memory page. Each DS28CN01 has a guaranteed unique factory-programmed 64-bit registration number. Communication with the DS28CN01 is accomplished through an industry standard I²C- and SMBus™-compatible interface. The SMBus timeout feature resets the device's
interface if a bus-timeout fault condition is detected.
Key Features
Applications/Uses
1024 Bits of EEPROM Memory Partitioned Into Four Pages of 256 Bits
Dedicated Hardware-Accelerated SHA Engine for Generating SHA-1 MACs
EEPROM Memory Pages can be Individually Copy-Protected or Put Into an EPROM Mode (Program from 1 to 0 Only)
Write Access Requires Knowledge of the Secret and the Capability of Computing and Transmitting a 160-Bit MAC as Authorization
Unique, Factory-Programmed, and Tested 64-Bit Registration Number Assures Absolute Traceability Because No Two Parts are Alike
Endurance 200k Cycles at +25°C
Serial Interface User Programmable for I²C Bus and SMBus Compatibility
Supports 100kHz and 400kHz I²C Communication Speeds
Download
E-Mail
